Texas Instruments Xilinx UG230, Руководство пользователя

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80 www.xilinx.com Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
Chapter 10: Analog Capture Circuit
R
Figure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communication to the other SPI peripherals. As shown in
Figure 10-6 , use a 34-cycle
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
UCF Location Constraints
Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
Figure 10-6: Analog-to-Digital Conversion Interface
Spartan-3E
FPGA
Master
D
1
D
2
D
3
D
0
D
5
D
6
D
7
D
4
D
9
D
10
D
11
D
8
D
13
D
12
D
1
D
2
D
3
D
0
D
5
D
6
D
7
D
4
D
9
D
10
D
11
D
8
D
13
D
12
Z
Z
Z
13 13 0 0
SPI_MISO
SPI_SCK
AD_CONV
13
Channel 0 Channel 0 Channel 1
Sample
point
Sample
point
Converted data is presented with a latency of one sample.
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
AD_CONV
SPI_SCK
SPI_MISO
Slave: LTC1407A-1 A/D Converter
Channel 1 Channel 0
UG230_c10_05_030306
Figure 10-7: Detailed SPI Timing to ADC
SPI_SCK
AD_CONV
SPI_MISO
13 12 11
High-Z
2 1 0
High-Z
6ns
8ns
3ns
4ns min
19.6ns min
45ns min
3
1 2 3
34
4
32
5
6
33 31 30
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
Channel 1
Channel 0
SPI_SCK
AD_CONV
SPI_MISO
UG230_c10_06_022306
Figure 10-8: UCF Location Constraints for the ADC Interface
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;