Test Procedure
7.7
Margin Example
In the default configuration file, all 24 rails are configured with the margining function. The pin assignments
are shown in the Configure page
→
Pin Assignment tab. Connect the onboard POL output voltage (J30) to
a rail’s MON pin using a jumper wire. Then connect the rail’s MARGIN pin to the onboard POL’s margin
input (J27) to close the margin loop. Connect the rail’s EN pin to J29 which controls the onboard POL’s
enable signal. Connect J28’s Pin 2 and Pin 3 using a shunt jumper. In the Fusion GUI
→
Monitor page,
turn on the CONTROL line. Observe that the rail’s EN pin LED is lit, and the onboard POL is enabled. The
POL’s output voltage is monitored in the Monitor page, which should be at 1.2 V.
In the Fusion GUI
→
Monitor page, click to change the margin status to Low. Observe that the POL output
voltage is regulated at Margin Low level defined in the Configure page
→
Vout Config tab. Click to change
the margin status to High. Observe that the POL output voltage is regulated at Margin High level.
7.8
Cascading Example
7.8.1
Sync Clock
Sync Clock can synchronize multiple UCD90240 devices such that they respond to the same GPI event
synchronously and the same GPI event has the same time stamp in all synchronized UCD90240 devices.
The Sync Clock I/O pin is located in J9. Implementing the Sync Clock feature requires two or more
UCD90240EVM-704 boards.
In the Fusion GUI
→
Configure page
→
Other Config tab, configure one EVM board as Sync Clock
master, and all other boards as slaves. Connect the multiple EVM boards to the same ground. Connect all
Sync Clock pins to the same node. Observe that the synchronized UCD90240 devices respond to the
same GPI event synchronously.
When the Sync Clock pin is not used, configure the UCD90240 device as Sync Clock master.
7.8.2
Fault Pin
Multiple UCD90240 devices can be acknowledged on the same rail fault and react accordingly, even if the
rail is monitored by only one UCD90240 device. This is achieved by the Fault Pin feature.
In each UCD90240 device, up to 4 GPI pins can be configured as Fault Pins. Each Fault Pin is connected
to a Fault Bus. Each Fault Bus is pulled up to 3.3 V by a 10-k
Ω
resistor. When there is no fault on a Fault
Bus, the Fault Pins are GPI pins and listen to the Fault Bus. When a rail fault is detected by a UCD90240
device, the corresponding Fault Pin is turned into active driven low state, pulling down the Fault Bus and
informing all other UCD90240 devices of the corresponding fault. Refer to the UCD90240 datasheet for
configuration and connection examples.
The Fault Pin feature and the Sync Clock feature can work together to achieve better synchronized fault-
response performance.
15
SLVUAF3A – March 2015 – Revised March 2015
UCD90240EVM-704 24-Rail Sequencer Development Board
Copyright © 2015, Texas Instruments Incorporated