// TVP5154A NTSC WSS/CGMS C-RAM Load Example
#define TVP5154A 0xB8;
// TVP5154A main I2C address
byte I2C_Data;
int CRAM_Address, count;
byte I2CData ={0x14,0x02};
// recommended WSS/CGMS settings
byte WSS_ARRAY[]={0x38,0,0x3F,0,0,0x71,0x6E,0x43,0x63,0x7C,0x08,0,0,0,0x39,0};
I2C_RegAddress = 0xD0;
// starting address of Line Mode registers
I2C_Data = 0xFF;
For (count = 0; count < 44; count ++)
{
I2CWriteByte(TVP5154A, I2C_RegAddress, I2C_Data);
//write FFh to Line Mode registers
I2C_RegA+;
}
I2CWriteByte(TVP5154A, 0xCF, 0);
// disable full field mode
CRAM_Address = 0x130;
// address of NTSC WSS/CGMS C-RAM block
I2CWriteByte(TVP5154A, 0xC4, 0x30);
// load C4h with C-RAM address[7:0]
I2CWriteByte(TVP5154A, 0xC5, 0x01);
// load C5h with C-RAM address[8]
For (count = 0; count < 16; count++)
{
I2CWriteByte(TVP5154A, 0xC3, WSS_ARRAY[count]);
// write 16 bytes of WSS/CGMS C-RAM
}
// data to register C3h.
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Line Mode Registers
Configuration RAM I
2
C Access Registers
Address
C3h-C5h
Address
7
6
5
4
3
2
1
0
C3h
Configuration data
C4h
RAM address [7:0]
C5h
Reserved
RAM
address 8
Example: (Write 2 data bytes starting at C-RAM address 130h).
1. Set C-RAM starting address.
(a) Write 30h to register C4h (C-RAM address [7:0]).
(b) Write 01h to register C5h (C-RAM address [8]).
2. Write the two bytes (38h and 00h)
(a) Write 38h to register C3h. Write first byte to C-RAM address 130h.
(b) Write 00h to register C3h. Write next byte to C-RAM address 131h.
Figure 2. Example Load of WSS/CGMS Configuration RAM
3
Line Mode Registers
After the VDP Configuration RAM is loaded, the Line Mode Registers (D0h-FBh) must be properly
configured for the desired VBI data service. Each register in this register bank is linked to a specific video
line number and video field. Video lines 6 through 27 of both Field 1 and Field 2 are supported. For each
desired data service, the proper mode configuration bits need to be loaded into the line mode register that
is linked to the correct video line number. Additional data slicing options such as filtering, error correction,
and FIFO routing are also available in the line mode registers. Unused line mode and line address
registers must be programmed with FFh. A detailed description of these registers is shown in Appendix A.
The TVP5154A VDP is based on an NTSC line numbering convention, resulting in a 3-line VDP offset
5
SLEA104 – July 2010
TVP5154A VBI Quick Start
Copyright © 2010, Texas Instruments Incorporated
