/////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////
// These commands can be used with the WinVCC4 EVM software to configure the Line Mode
// registers for a typical NTSC VBI setup.
// The WR_REG commands are direct writes to the I2C registers.
// Each command shown writes 1 byte to the I2C address
// specified in the command line.
BEGIN_DATASET
DATASET_NAME,"TVP5154A NTSC VDP/VBI SETUP"
INCLUDE, VDPRegsIdle.inc
// Set VDP registers to their default state
INCLUDE, SlicerRAM_601.inc
// Load VDP configuration RAM
WR_REG,VID_DEC,0x01,0xD8,0x44
// Line10 (Field 1)-TTX NTSC
WR_REG,VID_DEC,0x01,0xD9,0x44
// Line10 (Field 2)-TTX NTSC
WR_REG,VID_DEC,0x01,0xE0,0x0B
// Line14 (Field 1)-VITC NTSC
WR_REG,VID_DEC,0x01,0xE1,0x0B
// Line14 (Field 2)-VITC NTSC
WR_REG,VID_DEC,0x01,0xEC,0x09
// Line20 (Field 1)-WSS/CGMS NTSC
WR_REG,VID_DEC,0x01,0xED,0x09
// Line20 (Field 2)-WSS/CGMS NTSC
WR_REG,VID_DEC,0x01,0xEE,0x07
// Line21 (Field 1)-CC NTSC
WR_REG,VID_DEC,0x01,0xEF,0x07
// Line21 (Field 2)-CC NTSC
WR_REG,VID_DEC,0x01,0xCD,0x01
// Enable FIFO access, disable ANC data
WR_REG,VID_DEC,0x01,0xCB,0x4E
// Set Pixel Alignment [7:0] to 4Eh
WR_REG,VID_DEC,0x01,0xCC,0x00
// Set Pixel Alignment [9:8] to 0
END_DATASET
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////
// These commands can be used with the WinVCC4 EVM software to configure the Line Mode
// registers for a typical PAL VBI setup.
For PAL systems, the Line Mode register has
// a +3 line offset relative to the actual line number.
Each command shown writes
// 1 byte to the I2C address specified in the command line.
/////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////
BEGIN_DATASET
DATASET_NAME,"TVP5154A PAL VDP/VBI SETUP"
INCLUDE, VDPRegsIdle.inc
// Set VDP registers to their default FFh state
INCLUDE, SlicerRAM_601.inc
// Load VDP configuration RAM
WR_REG,VID_DEC,0x01,0xD8,0x41
// Line10 (Field 1)-TTX-B PAL(Line7)
WR_REG,VID_DEC,0x01,0xD9,0x41
// Line10 (Field 2)-TTX-B PAL (Line7
WR_REG,VID_DEC,0x01,0xEA,0x0C
// Line19 (Field 1)-VPS PAL (Line 16)
WR_REG,VID_DEC,0x01,0xEB,0x0C
// Line19 (Field 2)-VPS PAL (Line 16)
WR_REG,VID_DEC,0x01,0xF0,0x0A
// Line22 (Field 1)-VITC PAL(Line 19)
WR_REG,VID_DEC,0x01,0xF1,0x0A
// Line22 (Field 2)-VITC PAL(Line 19)
WR_REG,VID_DEC,0x01,0xF6,0x06
// Line25 (Field 1)-CC PAL(Line 22)
WR_REG,VID_DEC,0x01,0xF7,0x06
// Line25 (Field 2)-CC PAL(Line 22)
WR_REG,VID_DEC,0x01,0xF8,0x08
// Line26 (Field 1)-WSS/CGMS PAL(Line 23)
WR_REG,VID_DEC,0x01,0xF9,0x08
// Line26 (Field 2)-WSS/CGMS PAL(Line 23)
WR_REG,VID_DEC,0x01,0xCD,0x01
// Enable FIFO access, disable ANC data
WR_REG,VID_DEC,0x01,0xCB,0x4E
// Set Pixel Alignment [7:0] to 4Eh
WR_REG,VID_DEC,0x01,0xCC,0x00
// Set pixel Alignment [9:8] to 0
END_DATASET
/////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////
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Appendix B Sample WinVCC CMD File for VBI Setup
20
TVP5154A VBI Quick Start
SLEA104 – July 2010
Copyright © 2010, Texas Instruments Incorporated
