Texas Instruments TSW4200 Скачать руководство пользователя страница 5 | Manualshive

Страница: 5 / 12

Texas Instruments TSW4200 Скачать руководство пользователя страница 5

Software

Table 3. TSW4200-ADC Default Jumper Setting

Jumper

Default Position

Purpose

JP11

1-2 (parallel)

ADS62P49 (U2) parallel or serial mode option

JP8

1-2 (parallel)

SCLK parallel or serial mode option

JP12

1-2 (0dB gain, int. ref.)

SCLK parallel mode select

JP9

1-2 (parallel)

SDATA parallel or serial mode option

JP13

Open

SDATA parallel mode option

JP10

1-2 (parallel)

SEN parallel or serial mode select

JP14

1-2 (2's complement & DDR LVDS) SEN parallel mode option

JP20

1-2

CDCE72010 (U10) AUX select

JP21

1-2

CDCE72010 (U10) MODE select

J14

Open

CDCE72010 (U10) power down

J15

Open

CDCE72010 (U10) reset

JP3

2-3 (Off)

THS4509 (U1) power down

JP23

1-2

USB microcontroller (U6) power select

J18

Open

VCXO (VCXO1) enable

JP16

1-2

Power option (see schematic or ADS62PXX EVM user's guide)

JP17

Open

Power option (see schematic or ADS62PXX EVM user's guide)

JP19

1-2

Power option (see schematic or ADS62PXX EVM user's guide)

JP15

1-2

Power option (see schematic or ADS62PXX EVM user's guide)

JP18

1-2

Power option (see schematic or ADS62PXX EVM user's guide)

JP22

1-2

FPGA SDOUT path

JP5

1-2 (Low)

ADS62P49 (U2) CTRL3

JP6

1-2 (Low)

ADS62P49 (U2) CTRL2

JP7

1-2 (Low)

ADS62P49 (U2) CTRL1

2

Software

See the DAC3283 and the ADS62P49 EVM user’s guide for more detailed explanations of the EVM setup
and operation. This document assumes that EVM software applications are installed and functioning
properly.

Be sure to use the latest EVM software available at

. For the TSW4200 Demonstration Kit

evaluation, only the DAC3283 EVM software is needed. The ADS62P49 EVM software is optional since
the on-board jumpers provide sufficient control of the ADC.

5

SLWU071C – April 2010 – Revised November 2012

TSW4200 Demonstration Kit

Submit Documentation Feedback

Copyright © 2010–2012, Texas Instruments Incorporated

«
...
3
4
5
6
7
...
»

Содержание TSW4200

Страница 1: ...s 1 TSW4200 Demonstration Kit 2 2 DAC3283 EVM Block Diagram 3 3 ADS62P49 EVM Block Diagram 4 4 DAC3283 EVM Software Configuration 6 List of Tables 1 TSW4200 Demonstration Kit Reference Materials 2 2 TSW4200 DAC Default Jumper Setting 4 3 TSW4200 ADC Default Jumper Setting 5 1 SLWU071C April 2010 Revised November 2012 TSW4200 Demonstration Kit Submit Documentation Feedback Copyright 2010 2012 Texas...

Страница 2: ... Materials Device Data Sheet EVM User s Guide TSW4200 DAC DAC3283 SLAS693 DAC328xEVM SLAU311 TSW4200 ADC ADS62P49 SLAS635 ADS62PxxEVM SLAU237 The included FMC adapters are the FMC DAC Adapter and the FMC ADC Adapter They are a type of passive interconnect board enabling direct connection of the output of TI s LVDS high speed DACs or ADCs to a standard FMC interconnect header The FMC interconnect h...

Страница 3: ...nel outputs that go through a filter network and transformer to J3 Ch A and J1 Ch B c Clock Option The on board CDCDE62005 provides clocks to all the on board devices i The default DAC clock is configured at 614 4 MHz The DAC interpolation FPGA clock TSW3100 CLK and the FIFO OSTR clock can be configured based on the data rate FPGA configuration and system requirement For more information please re...

Страница 4: ...power supply input to power supply jack J17 For proper EVM operation and to prevent damage to the EVM only use a 5 V power supply b Analog Input Option The on board ADS62P49 has dual channel transformer coupled inputs from J3 Ch A and J6 Ch B c Clock Option The on board CDCE72010 provides a crystal filtered LVCMOS clock at 245 76 MHz to the on board ADS62P49 The reference clock input of 19 2 MHz t...

Страница 5: ...wer option see schematic or ADS62PXX EVM user s guide JP19 1 2 Power option see schematic or ADS62PXX EVM user s guide JP15 1 2 Power option see schematic or ADS62PXX EVM user s guide JP18 1 2 Power option see schematic or ADS62PXX EVM user s guide JP22 1 2 FPGA SDOUT path JP5 1 2 Low ADS62P49 U2 CTRL3 JP6 1 2 Low ADS62P49 U2 CTRL2 JP7 1 2 Low ADS62P49 U2 CTRL1 2 Software See the DAC3283 and the A...

Страница 6: ... instructions to the DAC3283 EVM d Toggle the Initialize button This initializes the CDCE62005 clock e Verify that the CDCE62005 LED D4 is illuminated indicating lock 2 For the ADC EVM connect the 5 V supply to J17 The USB connection to ADC EVM is optional The default ADS62P49 operates with internal reference and has 2 s complement LVDS output 3 Connect the ADC and DAC EVMs to the FPGA solution th...

Страница 7: ... Xilinx UG472 Multi Region Clocking The use case Driving Multiple BUFRs with Divide and BUFIO in particular provides extensive details over the implementation In an actual end user system implementation ADC and DAC connections to the FPGA should utilize a single FPGA IO bank for a simpler approach For an ADC with serial LVDS output implementation half of an IO bank can handle all connections from ...

Страница 8: ...ring the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warranted for the remainder of the original warranty period Replaced EVMs shall be warranted for a new full ninety 90 day warranty period 3 ...

Страница 9: ... by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la rég...

Страница 10: ... connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even with the inputs and outputs kept within the specified allowable ranges some circuit components may have elevated case temperatures These components include but are not limited to linear regulators switching transistors pass transistors cu...

Страница 11: ...F REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED 8 2 Specific Limitations IN NO EVENT SHALL T...

Страница 12: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

Отзывы:

Нет отзывов