Downloading Firmware Example
13
SLAU580B – June 2014 – Revised September 2016
Copyright © 2014–2016, Texas Instruments Incorporated
TSW14J10 FMC-USB Interposer Card
5
Downloading Firmware Example
If the FPGA development platform is to be programmed using the TSW14J10EVM, either connect the
provided ribbon cable between the TSW14J10 JTAG connector and the FPGA development platform
JTAG connector or move the shunts on JP2–JP5 to pins 2-3 if the JTAG signals are routed to the FMC
connector.
The HSDC Pro GUI software provides support for certain FPGAs and modes of operation. The firmware
files needed are special .svf formatted files for Xilinx devices and .rbf formatted files for Altera devices.
The files used by the GUI currently reside in the directory called "C:\Program Files (x86)\Texas
Instruments\High Speed Data Converter Pro\14J10KC705 Details\ Firmware" for the Xilinx Kintex KC705
board, "C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J10VC707 Details\
Firmware" for the Xilinx Virtex VC707 board, and "C:\Program Files (x86)\Texas Instruments\High Speed
Data Converter Pro\14J10ZC706 Details\ Firmware" for the Xilinx Zync ZC706 board.
To load a Xilinx KC705 development platform firmware after the GUI has established connection (setup as
shown in
), click on the
Select ADC
window in the top left of the GUI and select
ADS42JB69_LMF_421
, as shown in
The GUI asks if you want to update the Firmware for the ADC. Click on Yes. The GUI starts loading the
firmware from the PC to the Xilinx Kintex 7 FPGA. While the firmware is loading, the GPIO LED's on the
FPGA platform will all be on. This process takes about 2 minutes. Once completed, the INIT LED (DS21)
and DONE LED (DS20) will illuminate on the KC705. After the ADS42JBx9EVM is programmed, the
KC705 GPIO LED status will be as follows:
0 – On (DAC SYNC indicator)
1 – On (ADC SYNC indicator)
2 – Off (JESD reset)
3 – On (ADC JESD mode enabled)
4 – Off (DAC JESD mode enabled)
5 – Blinking (System clock divided down)
6 – Blinking (JESD Core clock divided down)
7 – Blinking (Reference clock divided down)
These same status LED's apply to the Xilinx VC707 development platform. For the Xilinx Zync ZC706
platform, only three status LED's are used. After this board is programmed and running with an ADC or
DAC, the status of the GPIO LED's will be as follows:
L - Blinking (Reference clock divided down)
C - Blinking (JESD Core clock divided down)
R - Blinking (System clock divided down)
If the ADS42Jx9EVM is not programmed, the GPIO LED status is as follows:
0 – On (DAC SYNC indicator)
1 – Off (ADC SYNC indicator)
2 – On (JESD reset)
3 – Off (ADC JESD mode enabled)
4 – Off (DAC JESD mode enabled)
5 – Blinking (System clock divided down)
6 – N/A (JESD Core clock divided down)
7 – N/A (Reference clock divided down)
