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SLOS743L – AUGUST 2011 – REVISED MARCH 2017
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Detailed Description
Copyright © 2011–2017, Texas Instruments Incorporated
Table 6-5. RX Special Setting Register (0x0A)
Function:
Sets the gains and filters directly
Default:
0x40 at POR = H or EN = L, and at each write to the ISO Control register (0x01). When bits B7, B6, B5 and B4 are all zero, the
filters are set for ISO/IEC 14443 B (240 kHz to 1.4 MHz).
Bit
Name
Function
Description
B7
C212
Band-pass 110 kHz to 570 kHz
Appropriate for 212-kHz subcarrier system (FeliCa)
B6
C424
Band-pass 200 kHz to 900 kHz
Appropriate for 424-kHz subcarrier used in ISO/IEC 15693
B5
M848
Band-pass 450 kHz to 1.5 MHz
Appropriate for Manchester-coded 848-kHz subcarrier used in
ISO/IEC 14443 A and B
B4
hbt
Band-pass 100 kHz to 1.5 MHz
Gain reduced for 18 dB
Appropriate for highest bit rate (848 kbps) used in high-bit-rate
ISO/IEC 14443
B3
gd1
00 = Gain reduction 0 dB
01 = Gain reduction for 5 dB
10 = Gain reduction for 10 dB
11 = Gain reduction for 15 dB
Sets the RX gain reduction and reduces sensitivity
B2
gd2
B1
Reserved
B0
Reserved
6.5
Receiver – Digital Section
The output of the TRF7970A analog receiver block is a digitized subcarrier signal and is the input to the
digital receiver block, which consists of two sections that partly overlap. The digitized subcarrier signal is a
digital representation of the modulation signal on the RF envelope. The two sections of the digital receiver
block are the
protocol bit decoder
section and the
framing logic
section.
The protocol bit decoder section converts the subcarrier coded signal into a serial bit stream and a data
clock. The decoder logic is designed for maximum error tolerance. This tolerance lets the decoder section
successfully decode even partly corrupted subcarrier signals that would otherwise be lost due to noise or
interference.
The framing logic section formats the serial bit stream data from the protocol bit decoder stage into data
bytes. During the formatting process, special signals such as the start of frame (SOF), end of frame
(EOF), start of communication, and end of communication are automatically removed. The parity bits and
CRC bytes are also checked and removed. The end result is "clean or raw" data that is sent to the 127-
byte FIFO register where it can be read by the external microcontroller system. Providing the data this
way, in conjunction with the timing register settings of the TRF7970A, means that the firmware developer
does not need to know the finer details of the ISO protocols to create a very robust application, especially
in low-cost platforms in which code space is at a premium and high performance is still required.
The start of the receive operation (successfully received SOF) sets the IRQ flags in the IRQ Status
register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13
(IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is
data to be read from the FIFO. The FIFO Status register (0x1C) should be used to provide the number of
bytes that should be clocked out during the actual FIFO read. Additionally, an interrupt is sent to the MCU
when the received data occupies 75% of the FIFO capacity to signal that the data should be removed
from the FIFO. By default, that interrupt is triggered once the received data packet is longer than 124
bytes. This setting can be modified in the Adjustable FIFO IRQ Levels register (0x14).
Any error in the data format, parity, or CRC is detected and notified to the external system by setting pin
13 (IRQ) to high. The source condition of the interrupt is available in the IRQ Status register (0x0C).
describes the bit coding description of this register. The information in the IRQ Status
register differs if the chip is configured as an RFID reader or as an NFC device (including card emulation).
describes NFC operation.
