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SLOS732G – JUNE 2011 – REVISED MARCH 2020
(1)
x = don't care
Table 6-3. Power Modes
(1)
MODE
EN2
EN
CHIP STATUS
CONTROL
REGISTER
(0X00)
REGULATOR
CONTROL
REGISTER
(0X0B)
TRANS-
MITTER
RECEIVER
SYS_CLK
(13.56 MHz)
SYS_CLK
(60 kHz)
VDD_X
TYPICAL
CURRENT
(mA)
TYPICAL
POWER
OUT (dBm)
TIME
(FROM
PREVIOUS
STATE)
Mode 4
(full power)
5 VDC
x
1
21
07
On
On
On
x
On
130
23
20 to 25 µs
Mode 4
(full power)
3.3 VDC
x
1
20
07
On
On
On
x
On
67
18
Mode 3
(half power)
5 VDC
x
1
31
07
On
On
On
x
On
70
20
20 to 25 µs
Mode 3
(half power)
3.3 VDC
x
1
30
07
On
On
On
x
On
53
15
Mode 2
5 VDC
x
1
03
07
Off
On
On
x
On
10.5
—
20 to 25 µs
Mode 2
3.3 VDC
x
1
02
00
Off
On
On
x
On
9
—
Mode 1
5 VDC
x
1
01
07
Off
Off
On
x
On
5
—
20 to 25 µs
Mode 1
3.3 VDC
x
1
00
00
Off
Off
On
x
On
3
Standby mode
5 VDC
x
1
81
07
Off
Off
On
x
On
3
—
4.8 ms
Standby mode
3.3 VDC
x
1
80
00
Off
Off
On
x
On
2
—
Sleep mode
1
0
x
x
Off
Off
Off
On
On
0.120
—
1.5 ms
Power down
0
0
x
x
Off
Off
Off
Off
Off
<0.001
—
Start