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SLWS245B – MAY 2014 – REVISED FEBRUARY 2017
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Copyright © 2014–2017, Texas Instruments Incorporated
Table 12. Register 6
Register 6
Bit Name
Reset Value
Description
Bit0
ADDR<0>
0
Register Address Bits
Bit1
ADDR<1>
1
Bit2
ADDR<2>
1
Bit3
ADDR<3>
1
Bit4
ADDR<4>
0
Bit5
RSV
0
Reserved
Bit6
RSV
0
Bit7
VCO_TRIM<0>
0
VCO capacitor array control bits;
used in manual cal mode
Bit8
VCO_TRIM<1>
0
Bit9
VCO_TRIM<2>
0
Bit10
VCO_TRIM<3>
0
Bit11
VCO_TRIM<4>
0
Bit12
VCO_TRIM<5>
1
Bit13
EN_LOCKDET
0
Enable monitor of lock detector output for autocal mode
Bit14
VCO_TEST_MODE
0
Counter mode, measure max and min freq for each VCO
Bit15
CAL_BYPASS
0
Bypass auto-cal; sets VCO_SEL and VCO_TRIM from Serial
interface
Bit16
MUX_CTRL<0>
1
Select signal for test output:
[001] = LD, [010] = NDIV, [100] = RDIV, [110] = A_counter
Bit17
MUX_CTRL<1>
0
Bit18
MUX_CTRL<2>
0
Bit19
ISOURCE_SINKB
0
Offset current polarity
Bit20
ISOURCE_TRIM<0>
0
Adjust Isource bias current in frac-n mode.
Bit21
ISOURCE_TRIM<1>
0
Bit22
ISOURCE_TRIM<2>
1
Bit23
LO_DIV_SEL<0>
0
Adjust LO path divider:
[00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8
Bit24
LO_DIV_SEL<1>
0
Bit25
LO_DIV_BIAS<0>
0
Adjust LO divider bias current:
[00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA
Bit26
LO_DIV_BIAS<1>
1
Bit27
TX_DIV_SEL<0>
0
Adjust TX path divider.
Bit28
TX_DIV_SEL<1>
1
[00] = Div/1, [01] = Div/2, [10] = Div/4. [11] = Div/8
Bit29
TX_DIV_BIAS<0>
0
Adjust TX divider bias current:
[00] = 25 uA, [01] = 37.5 uA, [10] = 50 uA, [11] = 62.5 uA
Bit30
TX_DIV_BIAS<1>
1
Bit31
GAIN_CTRL
0
Modulator gain control: [0] = Default, [1] = High Gain