2.1.6 J1 (PG)
J1 (PG) is a 2-pin header used for the power-good (PG) feature of the TPS7A57 LDO.
When the 2-pin shunt is placed across the header, the PG pin is pulled up to VOUT using a 100-kΩ resistor.
For more information regarding PG functionality, see the
.
2.2 Optional Load Transient Input and Output Connector Descriptions
2.2.1 VCC and GND
VCC (J7) and GND (J8) are the connection terminals for the input supply of the load transient circuit. The VCC
terminal is the positive connection, and the GND terminal is the negative (that is, ground) connection.
2.2.2 J17
J17 is an optional connection for the user to make measurements or apply DC loads to the output of the LDO.
2.2.3 TP10
TP10 is a test point that allows measurements of the load transient MOSFET drain voltage.
2.2.4 IN1
IN1 is the connection for the function generator to drive the gate driver device. IN1 is terminated by the 50-Ω
resistor, R22.
2.2.5 J15
J15 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
gate to source voltage. Alternatively, J15 can be used to toggle the load transient MOSFET on and off by using a
function generator if gate driver functionality is not desired.
2.2.6 TP11 and TP12
TP11 and TP12 allow the user to measure the gate drive resistance R21 when power is turned off to the EVM.
The user can also measure the voltage before and after R21 when the gate driver is used.
2.2.7 J6 and TP13
TP13 is the enable pin to enable the gate driver device. Tie this pin to GND by creating a solder-short on J6 to
enable the gate driver.
Setup
4
TPS7A57EVM-056 Evaluation Module
Copyright © 2022 Texas Instruments Incorporated
