![Texas Instruments TMS320x281 series Скачать руководство пользователя страница 29](http://html1.mh-extra.com/html/texas-instruments/tms320x281-series/tms320x281-series_reference-manual_1095203029.webp)
2.4
Transmission-Request-Reset Register (CANTRR)
www.ti.com
Transmission-Request-Reset Register (CANTRR)
These bits can only be set by the CPU and reset by the internal logic. These bits are reset when a
transmission is successful or is aborted. If the CPU tries to set a bit while the CAN tries to clear it, the bit
is set.
Setting the TRR[
n
] bit of the message object
n
cancels a transmission request if it was initiated by the
corresponding bit (TRS[
n
]) and is not currently being processed. If the corresponding message is currently
being processed, the bit is reset when a transmission is successful (normal operation) or when an aborted
transmission due to a lost arbitration or an error condition is detected on the CAN bus line. When a
transmission is aborted, the corresponding status bit (AA.31-0) is set. When a transmission is successful,
the status bit (TA.31-0) is set. The status of the transmission request reset can be read from the TRS.31-0
bit.
The bits in CANTRR are set by writing a 1 from the CPU.
Figure 2-4. Transmission-Request-Reset Register (CANTRR)
31
0
TRR[31:0]
RS-0
LEGEND: RS = Read/Set; -
n
= value after reset
Table 2-4. Transmission-Request-Reset Register (CANTRR) Field Descriptions
Bit
Field
Value
Description
31:0
TRR[31:0]
Transmit-request-reset bits
1
Setting TRR
n
cancels a transmission request
0
No operation
SPRU074F – May 2002 – Revised January 2009
eCAN Registers
29