Texas Instruments TMS320VC5509, Справочное руководство

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Sample Rate Generator Registers (SRGR1 and SRGR2)
12-29 McBSP Registers SPRU592E
Table 12 − 8. SRGR2 Bit Descriptions (Continued)
Bit Description Description Value Field
13 CLKSM Sample rate generator input clock mode bit. The sample rate generator can
accept an input clock signal and divide it down according to CLKGDV to
produce an output clock signal, CLKG. The frequency of CLKG is:
CLKG frequency = (Input clock frequency) / ( 1)
CLKSM is used in conjunction with the SCLKME bit to determine the source
for the input clock.
A DSP reset selects the McBSP internal input clock as the input clock and
forces the CLKG frequency to 1/2 the McBSP internal input clock frequency.
0 The input clock for the sample rate generator is taken from the CLKS pin or
from the CLKR pin, depending on the value of the SCLKME bit of PCR:
SCLKME CLKSM
Input Clock For
Sample Rate Generator
0 0 Signal on CLKS pin
1 0 Signal on CLKR pin
1 The input clock for the sample rate generator is taken from the McBSP
internal input clock or from the CLKX pin, depending on the value of the
SCLKME bit of PCR:
SCLKME CLKSM
Input Clock For
Sample Rate Generator
0 1 McBSP internal input clock
1 1 Signal on CLKX pin