
Serial Port Control Registers (SPCR1 and SPCR2)
McBSP Registers
12-12
SPRU592E
2. SPCR2 Bit Descriptions (Continued)
Bit
Description
Value
Field
2
XEMPTY
Transmitter empty bit. XEMPTY is cleared when the transmitter is ready to
send new data but no new data is available (transmitter-empty condition).
Note:
This bit has a negative polarity; a transmitter-empty condition is
indicated by XEMPTY = 0.
0
Transmitter-empty condition
Typically this indicates that all the bits of the current word have been
transmitted but there is no new data in DXR1. XEMPTY is also cleared if the
transmitter is reset and then restarted.
1
No transmitter-empty condition
1
XRDY
Transmitter ready bit. XRDY is set when the transmitter is ready to accept
new data in DXR[1,2]. Specifically, XRDY is set in response to a copy from
DXR1 to XSR1.
If the transmit interrupt mode is XINTM = 00b, the McBSP sends a transmit
interrupt (XINT) request to the CPU when XRDY changes from 0 to 1.
Also, when XRDY changes from 0 to 1, the McBSP sends a transmit
synchronization event (XEVT) signal to the DMA controller.
0
Transmitter not ready
When DXR1 is loaded, XRDY is automatically cleared.
1
Transmitter ready: DXR[1,2] is ready to accept new data.
Important:
If both DXRs are needed (word length larger than 16 bits), the
CPU or the DMA controller must load DXR2 first and then load DXR1. As
soon as DXR1 is loaded, the contents of both DXRs are copied to the
transmit shift registers (XSRs), as described in the next step. If DXR2 is not
loaded first, the previous content of DXR2 is passed to the XSR2.
0
XRST
Transmitter reset bit. You can use XRST to take the McBSP transmitter into
and out of its reset state.
Note:
This bit has a negative polarity; XRST = 0
indicates the reset state.
0
If you read a 0, the transmitter is in its reset state.
If you write a 0, you reset the transmitter.
1
If you read a 1, the transmitter is enabled.
If you write a 1, you enable the transmitter by taking it out of its reset state.
Содержание TMS320VC5509
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