
Serial Port Control Registers (SPCR1 and SPCR2)
12-5
McBSP Registers
SPRU592E
Table 12
−
1. SPCR1 Bit Descriptions
Bit
Field
Value
Description
15
DLB
Digital loopback mode bit. DLB disables or enables the digital loopback
mode of the McBSP:
0
Disabled
Internal DR is supplied by the DR pin. Internal FSR and internal CLKR can
be supplied by their respective pins or by the sample rate generator,
depending on the mode bits FSRM and CLKRM.
1
Enabled
Internal receive signals are supplied by internal transmit signals:
DR connected to DX
FSR connected to FSX
CLKR connected to CLKX
Internal DX is supplied by the DX pin. Internal FSX and internal CLKX are
supplied by their respective pins or are generated internally, depending on
the mode bits FSXM and CLKXM.
This mode allows you to test serial port code with a single DSP. The McBSP
transmitter directly supplies data, frame synchronization, and clocking to
the McBSP receiver.
14–13
RJUST
Receive sign-extension and justification mode bits. During reception,
RJUST determines how data is justified and bit filled before being passed
to the data receive registers (DRR1, DRR2).
Note:
RJUST is ignored if you enable a companding mode with the
RCOMPAND bits. In a companding mode, the 8-bit compressed data in
RBR1 is expanded to left-justified 16-bit data in DRR1.
00b
Right justify the data and zero fill the MSBs.
01b
Right justify the data and sign-extend the data into the MSBs.
10b
Left justify the data and zero fill the LSBs.
11b
Reserved (do not use)
Содержание TMS320VC5509
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