Texas Instruments TMS320VC5509, Справочное руководство

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Setting the Receive Data Delay
Receiver Configuration 7-18 SPRU592E
Figure 7 − 12. Range of Programmable Data Delay
B5 B6 B7
B4 B5 B6 B7
B3 B4 B5 B6 B7
Data delay 2
D(R/X)
Data delay 1
D(R/X)
Data delay 0
D(R/X)
FS(R/X)
CLK(R/X)
1-bit delay
Á
Á
Á
Á
ÁÁ
ÁÁ
0-bit delay
2-bit delay
7.13.2 0-Bit Data Delay
Normally, a frame-sync pulse is detected or sampled with respect to an edge
of internal serial clock CLK(R/X). Therefore, on the following cycle or later
(depending on the data delay value), data may be received or transmitted.
However, in the case of 0-bit data delay, the data must be ready for reception
and/or transmission on the same serial clock cycle.
This problem is solved for reception because receive data is sampled on the
first falling edge of CLKR where an active-high internal FSR is detected.
However, data transmission must begin on the rising edge of the internal CLKX
clock that generated the frame synchronization. Therefore, the first data bit is
assumed to be present in XSR1, and thus on DX. The transmitter then
asynchronously detects the frame-sync signal (FSX) going active high and
immediately starts driving the first bit to be transmitted on the DX pin.
7.13.3 2-Bit Data Delay
A data delay of two bit periods allows the serial port to interface to different
types of T1 framing devices where the data stream is preceded by a framing
bit. During reception of such a stream with a data delay of two bits (framing bit
appears after a 1-bit delay and data appears after a 2-bit delay), the serial port
essentially discards the framing bit from the data stream, as shown in
Figure 7
− 13. In this figure, the data transferred is an 8-bit value with bits
labeled B7, B6, B5, and so on.