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Texas Instruments TMS320F28004 Series, Руководство пользователя

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A.

Prefix X is used in orderable part numbers.

Figure 2-3. Example of Device Nomenclature

Nomenclature, Package Symbolization, and Revision Identification

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6

TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0

SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022

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Содержание TMS320F28004 Series

Страница 1: ...and Advisories 40 5 1 Silicon Revision 0 Usage Notes 40 5 2 Silicon Revision 0 Advisories 40 6 Documentation Support 42 7 Trademarks 42 8 Revision History 42 List of Figures Figure 2 1 Examples of Dev...

Страница 2: ...puts in GPIO Asynchronous Mode Yes Yes Yes VDD Supply VDD Supply During VDDIO Power Up VDD May Also Rise Yes Yes Yes eCAP eCAP HRFRC is Not EALLOW Protected Yes Yes Yes PLL PLL PLL May Not Lock on the...

Страница 3: ...Yes Yes ROM ROM Flash API Library and FPU32 Twiddle Factor RFFT Table Not Present Yes Yes REVID REVID Some TMX Revision A Devices Have an Incorrect REVID Value Yes GPIO GPIO X2 GPIO18 Pin Pullup Curr...

Страница 4: ...ed development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes Pr...

Страница 5: ...Code 2 Digit Year Month Code Assembly Lot Assembly Site Code Wafer Fab Code one or two characters as applicable Silicon Revision Code Green Low Halogen and RoHS compliant G4 F280049 YMLLLLS RSHS TI P...

Страница 6: ...e Nomenclature Nomenclature Package Symbolization and Revision Identification www ti com 6 TMS320F28004x Real Time MCUs Silicon Errata Silicon Revisions B A 0 SPRZ439G JANUARY 2017 REVISED AUGUST 2022...

Страница 7: ...pt is triggered depends on the configuration and timing of the other interrupts in the system This is expected to be a rare or nonexistent event in most applications If it happens the unwanted interru...

Страница 8: ...erformed by a VCU instruction VMOV32 and one write performed by an FPU instruction MOV32 If a pipeline stall occurs during the first write then the second write can corrupt the data If the first instr...

Страница 9: ...the nesting feature then the user must disable the interrupts before exiting the ISR Failing to do so may cause undefined behavior of CPU execution www ti com Silicon Revision B Usage Notes and Adviso...

Страница 10: ...the same register R6H as its source and a CPU register as the destination If a stall occurs in the E3 pipeline phase then MOV32 will read the value of R6H before the MPYF32 instruction completes Examp...

Страница 11: ...e is a Stall in the E3 Slot of the Instruction I1 Workaround Treat MPYF32 ADDF32 SUBF32 and MACF32 in this scenario as 3p cycle instructions Three NOPs or non conflicting instructions must be placed i...

Страница 12: ...ters E3 thus forwarding is not needed I5 I4 I3 I2 I1 There is no change due to the stall in the previous cycle I5 I4 I3 I2 I1 moves out of E3 and I5 moves to R2 R6H has the result of R5H R0H and is re...

Страница 13: ...vents will be triggered The spurious data ready event will trigger a corresponding CPU interrupt CLA task and DMA trigger if configured appropriately Workaround When SDFM data filter settings need to...

Страница 14: ...ple of SYSCLK This situation can be unavoidable if the clock sources for either the SD modulator or this device have a wide variation since a wide range of keep out frequencies become problematic If t...

Страница 15: ...ltaneous direction change will reset the counter properly and work as expected Workaround Do not use the PCRM 0 configuration if the direction change could occur while the index is active and the resu...

Страница 16: ...IO is greater than 1 ms when in internal VREG mode This does not impact device functionality once the external 1 2 V or internal 1 2 V supply begins to ramp See the TMS320F28004x Real Time Microcontro...

Страница 17: ...r is not required To enable software reuse on other devices where HRFRC is EALLOW protected using EALLOW and EDIS is recommended Workaround None www ti com Silicon Revision B Usage Notes and Advisorie...

Страница 18: ...commends doing lock sequences in succession until the PLL is in locked state when the PLL is configured for the first time after power up The lock sequence is disable the PLL start the PLL wait for th...

Страница 19: ...ional power reduction can be optionally achieved through software by one or all of these methods Decrease the SYSCLK frequency Change the SYSCLK source to OSCCLK by configuring SYSPLLCTL1 PLLCLKEN 0 C...

Страница 20: ...ons ends DCC operation prematurely TI recommends rerunning DCC if any of the below conditions are met DCCSTATUS DONE 1 and DCCCNT1 0 or DCCCNT0 0 or DCCVALID0 0 DCCSTATUS ERROR 1 and DCCCNT1 0 and DCC...

Страница 21: ...ed system behavior with other system components then do not use XRSn to drive other devices An external voltage supervisor can be used for these applications 3 For applications that need to avoid thes...

Страница 22: ...begins its ACK cycle This occurs because the slave may already be driving SDA low before the unexpected high level pulse occurs The glitch that occurs on SDA as a result of this short period of conten...

Страница 23: ...SDA MCU I2C I2C Figure 3 4 Placement of Series Termination Resistor and Pullup Resistor www ti com Silicon Revision B Usage Notes and Advisories SPRZ439G JANUARY 2017 REVISED AUGUST 2022 Submit Docum...

Страница 24: ...e Trip State Active State Trip State Active State Trip State Active State Figure 3 6 Resulting Undesired ePWM Outputs Possible Workaround Extend or reduce the blanking window to avoid any undesired tr...

Страница 25: ...of this drift the INTOSC1 and INTOSC2 internal oscillator frequencies could fall below the minimum values specified in the data sheet This would impact applications using INTOSC2 as the clock source...

Страница 26: ...n the receive buffer before the first data word is read NWORD packet with 16 words then the following sequence can be used Ignore RX buffer overrun RX_EVT_STS BUF_OVERRUN On RX_EVT_STS FRAME_DONE read...

Страница 27: ...which they were received If the order of the messages is critical to the application for processing then this behavior will prevent the proper use of the DCAN FIFO mode Workaround Use the DMA to read...

Страница 28: ...AUD to zero before calling the ROM SCI Bootloader Advisory Boot ROM MPOST Longer Boot Time With MPOST Enabled Revisions Affected 0 A B Details When MPOST functionality is enabled through user OTP the...

Страница 29: ...dresses 0x7F8 0x7FF should not be used for code Example 2 M0 ends at address 0x3FF and valid memory M1 follows it Code in M0 can be stored up to and including address 0x3FF Code can also cross into M1...

Страница 30: ...und will avoid this condition for any SYSCLK to OSCCLK ratio Workaround Add a software delay of 300 SYSCLK cycles using an NOP instruction after every write to the CLKSRCCTL1 register Example ClkCfgRe...

Страница 31: ...R when clearing the ADCINTFLG Check ADCINTOVF immediately after writing to ADCINTFLGCLR if it is set then write ADCINTFLGCLR a second time to ensure the ADCINTFLG is cleared The ADCINTOVF register wil...

Страница 32: ...e ADCINT trigger is set As a result the DMA could read a prior ADCRESULT value when the user expects the latest result if all of the following are true The ADC is in late interrupt mode The ADC operat...

Страница 33: ...ctive HLC channel Workaround Reorder the HLC instructions so that every PUSH instruction is followed by a non PUSH instruction The same applies for the PULL instruction If only one HLC channel is acti...

Страница 34: ...ate voltage level may be incorrectly interpreted as a high level if there is not sufficient logic filtering present in the receiver logic to filter this brief pulse Workaround If contention is a conce...

Страница 35: ...ll for the SCIFLR BUSY flag to set 2 Once the BUSY flag goes high poll for the SCIFLR RXRDY flag Concurrently within this loop also have a SW timeout which times out and exits the loop if the RXRDY fl...

Страница 36: ...3 should be written to ANAREFPP 56 pin RSH package The value 0x0003 should be written to ANAREFPP Advisory Analog Trim of Some TMX Devices Revisions Affected 0 A Details Some TMX samples may not have...

Страница 37: ...m can be generated by following the instructions in the ADC Zero Offset Calibration section of the TMS320F28004x Real Time Microcontrollers Technical Reference Manual If the internal oscillator trim c...

Страница 38: ...Real Time Microcontrollers Technical Reference Manual Workaround None Advisory REVID Some TMX Revision A Devices Have an Incorrect REVID Value Revision Affected A Details Some early TMX Revision A dev...

Страница 39: ...tch without compensating termination 2 The input sees large transients from external noise sources that rise above VDDIO 0 3 V at the pin 3 The input is driven by a device powered by a different volta...

Страница 40: ...con Revision B Advisories Advisory GPIO Pins may Drive High During Power Up Revision Affected 0 Details During power up the following pins will temporarily be in output mode and drive high These pins...

Страница 41: ...ing the condition Larger capacitors will be more effective at filtering the transient but must be balanced against the system level timing requirements of these pins For input pins a smaller capacitor...

Страница 42: ...Section 1 Usage Notes and Advisories Matrices Added section 2 Section 2 1 Device and Development Support Tool Nomenclature Updated section 4 Section 2 2 Devices Supported Added section 4 Section 2 3...

Страница 43: ...change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of thes...

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