Texas Instruments TMS320F28004 Series, Руководство пользователя

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Advisory Memory: Prefetching Beyond Valid Memory
Revisions Affected 0, A, B
Details The C28x CPU prefetches instructions beyond those currently active in its pipeline. If
the prefetch occurs past the end of valid memory, then the CPU may receive an invalid
opcode.
Workarounds M1, GS3 – The prefetch queue is 8 x16 words in depth. Therefore, code should not come
within 8 words of the end of valid memory. Prefetching across the boundary between two
valid memory blocks is all right.
Example 1: M1 ends at address 0x7FF and is not followed by another memory block.
Code in M1 should be stored no farther than address 0x7F7. Addresses 0x7F8–0x7FF
should not be used for code.
Example 2: M0 ends at address 0x3FF and valid memory (M1) follows it. Code in M0 can
be stored up to and including address 0x3FF. Code can also cross into M1, up to and
including address 0x7F7.
Flash – The prefetch queue is 16 x16 words in depth. Therefore, code should not
come within 16 words of the end of valid memory; otherwise, it generates a Flash ECC
uncorrectable error.
Table 3-1. Memories Impacted by
Advisory
MEMORY TYPE ADDRESSES IMPACTED
M1 0x0000 07F8–0x0000 07FF
GS3 0x0001 3FF8–0x0001 3FFF
Flash 0x0009 FFF0–0x0009 FFFF
www.ti.com Silicon Revision B Usage Notes and Advisories
SPRZ439G – JANUARY 2017 – REVISED AUGUST 2022
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TMS320F28004x Real-Time MCUs Silicon Errata
Silicon Revisions B, A, 0
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