Peripheral Bus
2-21
TMS320C6201/C6701 Program and Data Memory
2.7
Peripheral Bus
The peripherals are controlled by the CPU and the DMA controller through ac-
cesses of control registers. The CPU and the DMA controller access these reg-
isters through the peripheral data bus. The DMA controller directly accesses
the peripheral bus controller, whereas the CPU accesses it through the data
memory controller.
2.7.1
Byte and Halfword Access
The peripheral bus controller converts all peripheral bus accesses to word
accesses. However, on read accesses both the CPU and the DMA controller
can extract the correct portions of the word to perform byte and halfword ac-
cesses properly. Any side-effects caused by a peripheral control register read
occur regardless of which bytes are read. In contrast, for byte or halfword
writes, the values the CPU and the DMA controller only provide correct values
in the enabled bytes. The values that are always correct are shown in
Table 2–8. Undefined results are written to the nonenabled bytes. If you are
not concerned about the values in the disabled bytes, this is acceptable. Other-
wise, access the peripheral registers only via word accesses.
Table 2–8. Memory Contents After Little-Endian or Big-Endian Data Stores
Access
Type
Address Bits
(1:0)
Big-Endian
Register
Little-Endian
Memory Result
Word
00
XXXXXXXX
XXXXXXXX
Halfword
00
XXXX????
????XXXX
Halfword
10
????XXXX
XXXX????
Byte
00
XX??????
??????XX
Byte
01
??XX????
????XX??
Byte
10
????XX??
??XX????
Byte
11
??????XX
XX??????
Note:
X indicates nybbles correctly written, ? indicates nybbles with undefined value after
write