OMAP 2420 and the HWI Module
DSP/BIOS for OMAP 2420
D-5
D.3
OMAP 2420 and the HWI Module
With the introduction of the OMAP family of dual-core ARM + ‘C55x
devices, many more interrupt sources have been defined than can be
terminated on the legacy ‘C55x level 1 interrupt controller, which has a
limit of 32 interrupts. To accommodate additional interrupt sources, a
new interrupt mechanism has been provided in hardware: the "Level 2
Interrupt Controller" (L2IC).
The additional interrupts are prioritized and multiplexed by the Level 2
Interrupt Controller onto two dedicated level 1 interrupts. DSP/BIOS
internally configures all 32 level 2 interrupts to terminate on the single
level 1 FIQ interrupt. In the 24xx OMAP family, many peripherals that
formerly interrupted the DSP at level 1 have been moved out to level 2.
The L2IC contains a 32-bit Interrupt Mask Register (MIR), which defines
which level 2 interrupts are enabled or disabled.
The DSP/BIOS interface to the L2IC is implemented as part of the HWI
module. The following sections describe extensions made to the HWI
module to support the OMAP 2420.
D.3.1
Level 2 Interrupt Controller Base Address
By default, the Level 2 Interrupt Controller (L2IC) resides at data memory
address 0x7e4800. This coincides with the reset IOMA value of 0x3f. The
IO MAP (IOMA) base address is the page index used to access DSP I/O
space addresses from DSP memory space.
If you modify IOMA for any reason, you need to tell DSP/BIOS the new
base address for the L2IC. The following Tconf configuration property is
provided for this purpose:
bios.HWI.INTC_BASE = 0x7e4800; // 0x7e4800 is default
See the
OMAP 2410/2420 Technical Reference Manual
(SWPU064) for
details about programming IOMA.