Texas Instruments TMS320C28x, Справочное руководство

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Registers
C.2.1 CPU Register Changes
A brief description of the register modifications is given below. For a complete
description of each register, see descriptions in the C2xLP and C28x Refer-
ence Guides.
XT Multiplicand register. The 32-bit multiplicand register is called XT
on the C28x. The C2xLP TREG is represented by the upper 16 bits
(T). The lower 16 bit area is known as TL. The assembler will also
accept TH in place of T for the upper 16 bits of the XT register.
P Product register. This register is the same as the C2xLP PREG.
You can separately access the high half (PH) or the low half (PL) on
the C28x
ACC Accumulator. The size of ACC is the same on the C28x. Access to
the register has been enhanced. On C28x, you can access it as two
16-bit registers (AL and AH).
SP Stack Pointer. The SP is new on the C28x. It points directly to the
C28x software stack
XAR0 −
XAR7
Auxiliary registers. All of the auxiliary registers (XARn) are in-
creased to 32 bits on the C28x. This enables a full 32-bit address
reach in data space. Some instructions separately access the low
half of the registers (ARn).
PC Program counter. The PC is 22 bits on C28x. On the C2xLP, the PC
is 16 bits
RPC Return program counter. The RPC register is new on the C28x.
When a call operation is performed, the return address is saved in
the RPC register and the old value in the RPC is saved on the stack.
When a return operation is performed, the return address is read
from the RPC register and the value on the stack is written into the
RPC register. The net result is that return operations are faster (4
instead of 8 cycles). This register is only used when certain call and
return instructions are used. Normal call and return instructions by-
pass this register.
IER Interrupt enable register. The IER is analogous to the Interrupt
Mask Register (IMR) on the C2xLP. It performs the same function,
however, the name has changed to more appropriately describe the
function of the register. Each bit in the register enables one of the
maskable interrupts. On the C2xLP, there are six maskable CPU in-
terrupts. On the C28x CPU, there are 16 CPU interrupts. On the
C2xLP, the IMR was memory mapped.
DBGIER Debug interrupt-enable register. The DBGIER is new on the C28x.
It enables interrupts during debug events and allows the processor
and debugger to perform real-time emulation.
IFR Interrupt flag register. The IFR functions the same as on the C2xLP.
There are more valid bits in this register to accommodate the addi-
tional interrupts on the C28x. On the C2xLP, the IFR was memory
mapped.