Texas Instruments TMS320C28x, Справочное руководство

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CPU Registers
2-12
Figure 2 − 7. Address Reach of the Stack Pointer
0000 0000 − 0000 FFFF
0001 0000 − FFFF FFFF
Data memory
Range accessible
by way of SP
Range not accessible
by way of SP
The operation of the stack is as follows:
-
The stack grows from low memory to high memory.
-
The SP always points to the next empty location in the stack.
-
At reset, the SP is initialized, so that it points to address 0000 0400
16
.
-
When 32-bit values are saved to the stack, the least significant 16 bits are
saved first, and the most significant 16 bits are saved to the next higher
address (little endian format).
-
When 32-bit operations read or write a 32-bit value, the C28x CPU expects
the memory wrapper or peripheral-interface logic to align that read or write
to an even address. For example, if the SP contains the odd address
0000 0083
16
, a 32-bit read operation reads from addresses 0000 0082
16
and 0000 0083
16
.
-
The SP overflows if its value is increased beyond FFFF
16
or decreased
below 0000
16
. When the SP increases past FFFF
16
, it counts forward
from 0000
16
. For example, if SP = FFFE
16
and an instruction adds 3 to the
SP, the result is 0001
16
. When the SP decreases past 0000
16
, it counts
backward from FFFF
16
. For example, if SP = 0002
16
and an instruction
subtracts 4 from SP, the result is FFFE
16
.
-
When values are being saved to the stack, the SP is not forced to align with
even or odd addresses. Alignment is forced by the memory wrapper or pe-
ripheral-interface logic.
2.2.6 Auxiliary Registers (XAR0 − XAR7, AR0 − AR7)
The CPU provides eight 32-bit registers that can be used as pointers to
memory or as general-purpose registers (see Section 5.6,
Indirect Addressing