C
L1
(A)
C
L2
(A)
X2
X1/XCLKIN
Crystal
(a)
(b)
External Clock Signal
(Toggling 0-V
)
DD
X1/XCLKIN
X2
NC
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
www.ti.com
3.9
PLL-Based Clock Module
The F281x and C281x have an on-chip, PLL-based clock module. This module provides all the necessary
clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio
control to select different CPU clock rates. The watchdog module should be disabled before writing to the
PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes
131072 XCLKIN cycles.
The PLL-based clock module provides two modes of operation:
•
Crystal operation: This mode allows the use of an external crystal/resonator to provide the time base
to the device.
•
External clock source operation: This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1/XCLKIN pin.
A.
TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the
DSP chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also
advise the customer regarding the proper tank component values that will ensure start-up and stability over the entire
operating range.
Figure 3-10. Recommended Crystal/Clock Connection
Table 3-17. Possible PLL Configuration Modes
PLL MODE
REMARKS
SYSCLKOUT
Invoked by tying XPLLDIS pin low upon reset. PLL block is completely disabled.
PLL Disabled
Clock input to the CPU (CLKIN) is directly derived from the clock signal present at the
XCLKIN
X1/XCLKIN pin.
Default PLL configuration upon power-up, if PLL is not disabled. The PLL itself is
PLL Bypassed
bypassed. However, the /2 module in the PLL block divides the clock input at the
XCLKIN/2
X1/XCLKIN pin by two before feeding it to the CPU.
Achieved by writing a non-zero value “n” into PLLCR register. The /2 module in the
PLL Enabled
(XCLKIN * n) / 2
PLL block now divides the output of the PLL by two before feeding it to the CPU.
3.10 External Reference Oscillator Clock Option
The typical specifications for the external quartz crystal for a frequency of 30 MHz are listed below:
•
Fundamental mode, parallel resonant
•
C
L
(load capacitance) = 12 pF
•
C
L1
= C
L2
= 24 pF
•
C
shunt
= 6 pF
•
ESR range = 25 to 40
Ω
52
Functional Overview
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