RESETz
TAS_MCLK
TAS_WCLK
TAS_MISO
TAS_MOSI
TAS_SSz
TAS_SCLK
I2S_ENABLE
TAS_SDA
TAS_BCLK
TAS_DIN
TAS_SCL
ASI_S0
ASI_S1
I2S3_DOUT_SRC
DUT_RESETz
TAS_DOUT
I2S2_DOUT_SRC
I2S1_DOUT
+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.50k
R1
27.4
R2
27.4
R3
47pF/50V
C1
47pF/50V
C2
100k
R4
1.0uF/16V
C3
2
1
S4
0.1uF/16V
C4
0.1uF/16V
C5
LVC1G126DBVR
VCC
OE
A
GND
1
2
4
5
3
U3
0.1uF/16V
C7
0.1uF/16V
C8
1
2
S1
0.1uF/50V
C9
10k
R5
10k
R6
2
1
S2
0.1uF/16V
C10
0.1uF/50V
C11
1
2
S3
10k
R7
LED1
Yellow
649
R8
LED2
Yellow
649
R9
10k
R10
2
1
EE Program
JP2
0.1uF/16V
C13
R11
3.09k
1000pF/50V
C14
100pF/50V
C15
10k
R12
2.7k
R13
2.7k
R14
1
2
JP3
0.1uF/50V
C16
10k
R15
4.7k
R16
1
JP1
2
GND
4.7k
R17
L;DN
11
C
C
JOHN FEDAK IV
JANUARY 31, 2014
AIP013C_Schematic.sbk
DESIGN LEAD
PAGE INFO:
FILENAME
DATE
OF
DRAWN BY
SHEET
PCB REV
SCH REV
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
+3.3VIO
FB5
220ohms/2A
FB6
220ohms/2A
1
2
3
4
5
J1
Data+
GND
ID_NC
5v
Data-
+3.3VIO
1
2
3
4
Y1
6.0MHz
Vcc
OUT
OE
GND
+3.3VIO
GND
C6
0.1uF/16V
+3.3VIO
GND
U5
PowerPAD
24FC512-I/MF
GND
GND
C12
0.1uF/16V
+3.3VIO
+3.3VIO
+3.3VIO
U4
CBTLV3253DBQ
1
2
3
4
5
6
7
10
11
12
13
14
15
16
24FC512-I/MF
1
2
3
4
5
6
7
8
U5
GND
+3.3VIO
GND
TAS1020BPFB
U2
(ADC Data)
7
8
9
10
11
12
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
TAS1020B
USB HOST ADAPTER
TLV320AIC3268RGC EVALUATION BOARD
USB CONTROLLER
2
(DAC Data)
DUT RESET
APP
PATCH
USB RESET
USB INPUT
13 14 15 16 17 18 19 20 21 22 23 24
13 14 15 16 17 18 19 20 21 22 23 24
37
38
39
40
41
42
43
44
45
46
47
48
8
9
Y
TI
TLV320AIC3268EVM-U EVM Schematics
Figure 6. TAS1020BPFB USB Controller
9
SLAU564A – February 2014 – Revised February 2014
TLV320AIC3268EVM-U Evaluation Module
Copyright © 2014, Texas Instruments Incorporated