Texas Instruments TLC694 Series, Техническое справочное руководство

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BANK_SEL = 0
ES-PWM Decoder
Timing Control
Memory
BANK A
Write Grayscale Data
for Next Frame
VSYNC
16-bit Common Shift Register
MSB LSB
SCLK
SIN
SOUT
16-bit
Memory
BANK B
Read Grayscale Data
for Current Frame
16-bit
OUT0 to OUT15
BANK_SEL = 1
ES-PWM Decoder
Timing Control
Memory
BANK A
Read Grayscale Data
for Current Frame
VSYNC
16-bit Common Shift Register
MSB LSB
SCLK
SIN
SOUT
16-bit
Memory
BANK B
Read Grayscale Data
for Next Frame
16-bit
OUT0 to OUT15
Select BANK A Select BANK B
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Write Grayscale Data Into Memory
27 SLVUBF4A – February 2018 – Revised June 2019
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PWM Grayscale Control
TI Information — Selective Disclosure
Figure 3-1. BANK-Selection Exchange Operation
3.1.2 Detail of Memory BANK
Each memory BANK contains the frame-image grayscale data of all the 32 or 48 scan lines. Each line
comprises sixteen 16-bit-width memory units. Each memory unit contains the grayscale data of the
corresponding channel.
Depending on the number of scan lines set in function-control register 3 (FC3 bit 3 to bit 8), the total
number of memory units that must be written in one BANK is: 16 × the number of scan lines. For example,
if the number of scan lines is set to 32, then 512 (32 × 16 = 512) memory units must be written during
each frame period.
Figure 3-2 shows the detailed memory structure of the TLC694x device.