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Function-Control Registers

SLVUBF4A – February 2018 – Revised June 2019

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Function Control

TI Information — Selective Disclosure

Figure 2-5. FC4 Register

RESERVED

PWM_ALIGN2

RESERVED

R-0b

R/W-0b

R-0b

RESERVED

LGSE2

RESERVED

R-0b

R/W-0b

R-0000b

Table 2-8. FC4 Register Field Descriptions

Bit

Field

Type

Reset

Description

RESERVED

Reserved

PWM_ALIGN2

R/W

Set the PWM alignment mode in LGSC1 time.

0b = All PWM leading edges aligned at the beginning of each
LGSC1 time

1b = All PWM trailing edges aligned at the end of each LGSC1 time

13-6

RESERVED

00000000b

Reserved

5-4

LGSE2

R/W

00b

Set the low-grayscale de-coupling enhancement level. LGSE level
increases with register data setting from 00b to 11b.

00b = Lowest de-coupling enhancement

…

11b = Highest de-coupling enhancement

3-0

RESERVED

0000b

Reserved

Содержание TLC694 Series

Страница 1: ...TI Information Selective Disclosure TLC694x 16 Channel LED Driver Technical Reference Manual Technical Reference Manual Literature Number SLVUBF4A February 2018 Revised June 2019 ...

Страница 2: ...2 3 1 Global Brightness Control and Current Setting 20 2 3 2 LED Open Detection LOD 21 2 3 3 Precharge Function 24 2 3 4 Power Save Mode PSM 24 2 3 5 Thermal Shutdown TSD 25 2 3 6 IREF Resistor Short Protection ISP 25 3 PWM Grayscale Control 26 3 1 Write Grayscale Data Into Memory 26 3 1 1 Memory Structure Overview 26 3 1 2 Detail of Memory BANK 27 3 1 3 Write Grayscale Data Into One Memory Unit 2...

Страница 3: ...8 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Contents TI Information Selective Disclosure 4 2 1 Design Requirements 43 4 2 2 FC Registers Settings 44 4 2 3 PWM Grayscale Control 46 ...

Страница 4: ...etection Circuit 21 2 15 Bit Arrangement in the LOD Data Register 21 2 16 Read LOD Data 22 2 17 LED Open Detection Process 23 2 18 Caterpillar Issue 24 2 19 Power Save Mode 25 3 1 BANK Selection Exchange Operation 27 3 2 TLC694x Memory Unit Structure 28 3 3 Write Grayscale Data Into Selected Memory Unit 29 3 4 Write Grayscale Data Into Selected Memory BANK 30 3 5 Send VSYNC Command 31 3 6 Conventi...

Страница 5: ...rent Value 20 2 12 Maximum Constant Current vs External Resistor RIREF 20 2 13 Description of READLOD Command 22 3 1 WRTGS Command Description 29 3 2 VSYNC Command Description 31 4 1 TLC6946 Design Parameters 38 4 2 TLC6946 System Structure 39 4 3 SCLK and GCLK Frequency 39 4 4 Channel Current and Brightness Control Method 1 40 4 5 Channel Current and Brightness Control Method 2 40 4 6 Function Co...

Страница 6: ... for the data sheet rather a companion guide that should be used alongside the device specific data sheet to understand the details to program the device The primary purpose of the TRM is to abstract the programming details of the device from the data manual This allows the data sheet to outline the high level features of the device without unnecessary information about register descriptions or pr...

Страница 7: ...h density multiplexing LED matrix display and LED panel applications The TLC6946 and TLC6948 devices integrate enhanced circuits to solve the various display issues in fine pitch LED display applications the low grayscale uniformity issue coupling issue ghosting issue and caterpillar issue The TLC6946 and TLC6948 devices feature an LED open detection function and the error detection results can be...

Страница 8: ...mit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Introduction TI Information Selective Disclosure Grayscale Control Clock 33 MHz max Extended Grayscale Control Rate 50 MHz max Diagnostics and Protection LED Open Detection LOD IREF Resistor Short Protection ISP Thermal Shutdown TSD Intelligent Power Save Mode 1 3 Applications Mono Color Multi Color Full Color LED Displa...

Страница 9: ...UT15 SIN SCLK LAT GCLK IREF GND VCC SOUT TLC6948 Device 3 RIREF VCC Line 0 Line n Line 47 Controller SW 0 SW n SW 47 www ti com Typical Application Schematic 9 SLVUBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Introduction TI Information Selective Disclosure Figure 1 2 Typical Application Schematic of TLC6948 With 48 Multiplex...

Страница 10: ...UBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Function Control TI Information Selective Disclosure Chapter 2 SLVUBF4A February 2018 Revised June 2019 Function Control 2 1 Function Control Registers Function control registers are used to store the configuration information which controls the TLC694x operating mode There are fo...

Страница 11: ... Register 15 14 13 12 11 10 9 8 REVERSE INTERFERENCE R W 0110b R W 0110b 7 6 5 4 3 2 1 0 LGSE LODRM_EN LODVTH LGSE_E R W 0000b R W 1b R W 00b R W 0b Table 2 2 FC1 Register Field Descriptions Bit Field Type Reset Description 15 12 REVERSE R W 0110b Set the reverse voltage level at OUTn The OUTn voltage level decreases with register data settings from 0000b to 1111b 0000b Highest level 0110b Medium ...

Страница 12: ...3 FC2 Register Field Descriptions Bit Field Type Reset Description 15 13 LGSC1 R W 010b Set the low grayscale coupling improvement 1 level The LGSC1 function requires some GCLK periods during each display sub period See Table 2 4 for the details about LSGC1 GCLK periods 12 10 RESERVED R 000b Reserved 9 PCHG_DIS R W 0b Set the precharge function 0b Precharge function is enabled 1b Precharge functio...

Страница 13: ...eriods 10 GCLK periods 0 1 0 34 GCLK periods Default 18 GCLK periods Default 0 1 1 54 GCLK periods 28 GCLK periods 1 0 0 72 GCLK periods 36 GCLK periods 1 0 1 90 GCLK periods 46 GCLK periods 1 1 0 108 GCLK periods 54 GCLK periods 1 1 1 124 GCLK periods 62 GCLK periods 2 1 4 Function Control Register 3 FC3 Function control register 3 FC3 is used to set the BC scan line number and middle grayscale e...

Страница 14: ...out the number setting of TLC6946 scan lines Table 2 6 Number of TLC6946 Scan Lines SCAN_LINE NUMBER OF TLC6946 SCAN LINES BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 0 0 0 0 0 1 Default 0 0 0 0 1 2 0 0 0 1 0 3 0 1 1 1 1 16 1 1 1 0 1 30 1 1 1 1 0 31 1 1 1 1 1 32 Table 2 7 shows the details about the number setting of TLC6948 scan lines Table 2 7 Number of TLC6948 Scan Lines SCAN_LINE_48 SCAN_LINE NUMBER OF TLC6...

Страница 15: ...E2 RESERVED R 0b R 0b R W 0b R W 0b R 0000b Table 2 8 FC4 Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R 0b Reserved 14 PWM_ALIGN2 R W 0b Set the PWM alignment mode in LGSC1 time 0b All PWM leading edges aligned at the beginning of each LGSC1 time 1b All PWM trailing edges aligned at the end of each LGSC1 time 13 6 RESERVED R 00000000b Reserved 5 4 LGSE2 R W 00b Set the...

Страница 16: ... LAT IS HIGH DESCRIPTION WRTFC_EN 15 Enable the write function control data command This WRTFC_EN command must always be input before writing function control data Otherwise the device ignores the WRTFCx commands WRTFC1 5 Command to write function control data to the FC1 register The 16 bit function control data in the common shift register are copied to the FC1 register WRTFC2 7 Command to write ...

Страница 17: ...Feedback Copyright 2018 2019 Texas Instruments Incorporated Function Control TI Information Selective Disclosure Figure 2 7 WRTFC_EN Command and WRTFC2 Command Figure 2 8 WRTFC_EN Command and WRTFC3 Command Figure 2 9 WRTFC_EN Command and WRTFC4 Command 2 2 2 Read Function Control Register The TLC694x device also provides the method to read back the function control data from internal registers Si...

Страница 18: ... LAT IS HIGH DESCRIPTION READFC1 6 Command to read function control data from the FC1 register The 16 bit data in the FC1 data latch are copied to the common shift register at the falling edge of the LAT signal The loaded data can be read out from SOUT synchronized with the SCLK rising edge READFC2 8 Command to read function control data from the FC2 register The 16 bit data in the FC2 data latch ...

Страница 19: ... 11 12 16 15 14 13 16 bit FC3 Data FC3 Bit 15 READFC3 FC3 Bit 14 FC3 Bit 13 FC3 Bit 4 FC3 Bit 3 FC3 Bit 2 FC3 Bit 1 FC3 Bit 0 SCLK LAT FC3 SOUT 16 bit FC3 data are copied to 16 bit common shift register at the LAT falling edge 10 SCLK rising edges must be input while LAT is high www ti com Function Control Commands 19 SLVUBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright...

Страница 20: ...BC Data vs Constant Current Ratio and Set Current Value BC DATA GAIN RATIO OF GAIN GAIN_MAX AT MAX BC IOUT mA IOLCmax 25 mA TYP IOUT mA IOLCmax 2 4 mA TYP BINARY DECIMAL HEX 000 0000 0 00 4 12 5 3 13 0 3 000 0001 1 01 4 22 13 19 3 3 0 32 000 0010 2 02 4 44 13 88 3 47 0 33 011 0101 53 35 15 78 49 31 12 33 1 18 011 0110 Default 54 Default 36 Default 16 50 12 5 1 2 011 0111 55 37 16 22 50 69 12 67 1 ...

Страница 21: ...e 2 2 If the OUTn voltage is lower than the programmed voltage the corresponding output LOD bit is set to 1 to indicate an open LED Otherwise the output of that LOD bit is 0 LOD data output by the detection circuit are valid only during the on period of that OUTn output channel The LOD data are always 0 for outputs that are turned off Figure 2 14 shows the equivalent circuit of LED open detection ...

Страница 22: ...com 22 SLVUBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated Function Control TI Information Selective Disclosure Table 2 13 Description of READLOD Command COMMAND NAME NUMBER OF SCLK RISING EDGES WHEN LAT IS HIGH DESCRIPTION READLOD 13 Read LOD information command The 16 bit LOD data in the LOD holder is copied to the common shif...

Страница 23: ... Figure 2 17 shows the flow of the LED open detection process 1 N is the number of cascaded TLC694x devices Figure 2 17 LED Open Detection Process 2 3 2 4 Caterpillar Removal The caterpillar issue is a common phenomenon caused by broken LEDs LED open in multiplexing LED display applications The cause of this LED open caterpillar issue is that the electric charge on the parasitic capacitance of an ...

Страница 24: ...ue is eliminated until device reset or LODRM_EN is set to 0 The internal caterpillar elimination circuit can handle a maximum of three lines that have an open LED fault condition If there is an open LED located in three or fewer lines the TLC69x device is able to handle the open LEDs all in these lines If there are open LEDs in more than three lines the caterpillar issue is solved for the lines wh...

Страница 25: ...the default value of this bit is 0 When this function is enabled PSM_EN 1 if all the grayscale GS data received for the next frame are 0 then the device enters power save mode at the moment the VSYNC command is input When operating in the power save mode the device continuously detects whether non zero GS data is input for the next frame Among all the GS data for the next frame if any non zero dat...

Страница 26: ...play memory unit is divided into two BANKs BANK A and BANK B During the normal operation one BANK is selected for the current frame image display and the other BANK is used to write the next frame image data The BANK selection is determined by the BANK_SEL bit which is an internal flag register bit After power on BANK_SEL is initialized to 0 and BANK A is selected to be written into the next frame...

Страница 27: ...n Feedback Copyright 2018 2019 Texas Instruments Incorporated PWM Grayscale Control TI Information Selective Disclosure Figure 3 1 BANK Selection Exchange Operation 3 1 2 Detail of Memory BANK Each memory BANK contains the frame image grayscale data of all the 32 or 48 scan lines Each line comprises sixteen 16 bit width memory units Each memory unit contains the grayscale data of the corresponding...

Страница 28: ...Channel 1 Channel 2 Channel 15 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit...

Страница 29: ...By BANK_SEL Line Counter and Channel Address Counter WRTGS www ti com Write Grayscale Data Into Memory 29 SLVUBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated PWM Grayscale Control TI Information Selective Disclosure 3 1 3 Write Grayscale Data Into One Memory Unit If the TLC694x device detects one SCLK rising edge during the LAT ...

Страница 30: ...0 channel 1 LED of the TLC694x device When the second WRTGS command is received all the data in the common shift register is latched into the memory unit of BANK A line 0 channel 1 at the falling edge of LAT At the same time CHANNEL_COUNTER increments by 1 and LINE_WRITE_COUNTER stays the same Thus the memory unit of BANK A line 0 channel 2 is selected to be written with the data in the common shi...

Страница 31: ...iption COMMAND NAME NUMBER OF SCLK RISING EDGES WHEN LAT IS HIGH DESCRIPTION VSYNC 3 Vertical frame synchronization command When this command is received BANK_SEL toggles and all internal counters are reset to 0 A new frame image is displayed in the coming frame period Figure 3 5 Send VSYNC Command 3 2 2 Send VSYNC Command After all the grayscale GS data is written into the selected memory BANK th...

Страница 32: ...ivided into 256 display segments Each segment has 256 GCLK periods The output channel OUTn total on time during one frame display period is distributed evenly in these 256 segments By this means the visual refresh rate is increased by 256 times This is a good method for a static LED display system but not good for a multiplexed dynamic LED display system If one finishes all 256 segments of one sca...

Страница 33: ...2 OUTn GS 0000h OFF OUTn GS 0001h ON OUTn GS 0002h ON Segment 0 Segment 255 ON ON ON OUTn GS FFFEh ON OUTn GS FFFFh ON OFF OFF OFF ON OFF Conventional 8 8 Mode ES PWM Static Segment 1 Segment 63 Segment 64 Segment 127 Segment 128 Segment 191 Segment 192 Segment 254 256 GCLK 255 GCLK 63 256 GCLK 64 256 GCLK 64 256 GCLK 63 256 GCLK 1 GCLK ON ON Segment 0 Segment 255 Segment 1 Segment 63 Segment 64 S...

Страница 34: ...ay segments Each segment has 128 GCLK periods The output channel OUTn total on time during one frame display period is distributed evenly in these 512 segments By this means the visual refresh rate is increased by 512 times This is a good method for a static LED display system but not good for a multiplexed dynamic LED display system If one finishes all 512 segments of one scan line then changes t...

Страница 35: ...n GS 0000h OFF OUTn GS 0001h ON OUTn GS 0002h ON Segment 0 Segment 511 ON ON ON OUTn GS FFFEh ON OUTn GS FFFFh ON OFF OFF OFF ON OFF Conventional 7 9 Mode ES PWM Static Segment 1 Segment 127 Segment 128 Segment 255 Segment 256 Segment 383 Segment 384 Segment 510 128 GCLK 128 GCLK 127 128 GCLK 128 128 GCLK 128 128 GCLK 127 128 GCLK 1 GCLK ON ON Segment 0 Segment 511 Segment 1 Segment 127 Segment 12...

Страница 36: ...er PWM Control and New Frame Image Display www ti com 36 SLVUBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated PWM Grayscale Control TI Information Selective Disclosure Figure 3 11 TLC6948 Multiplexed 7 9 Mode of ES PWM 48 Multiplexing 3 3 3 Send GCLK for Multiplexing 3 3 3 1 GCLK for Each Sub Period When one bank of the display m...

Страница 37: ...exing www ti com PWM Control and New Frame Image Display 37 SLVUBF4A February 2018 Revised June 2019 Submit Documentation Feedback Copyright 2018 2019 Texas Instruments Incorporated PWM Grayscale Control TI Information Selective Disclosure Figure 3 13 shows an example for a 48 multiplexing LED display system Figure 3 13 Timing Sequence for 48 Multiplexing 3 3 4 Complete Frame Image Display When th...

Страница 38: ...6946 device to build an LED display board with 160 90 pixels 4 1 1 Design Requirements For this example use the following as the system design parameters Table 4 1 TLC6946 Design Parameters DESIGN PARAMETER EXAMPLE VALUE VCC and VLED value 3 8 V SIN SOUT SCLK LAT and GCLK voltage range Low level GND to 0 3 VCC high level 0 7 VCC to VCC Maximum current per LED IRED 5 mA IGREEN 2 mA IBLUE 1 mA PWM r...

Страница 39: ...s the minimum SCLK frequency fVR is the visual refresh rate of the entire cascading series fFPS is the frame rate per second m is the number of GCLKs for each sub period determined by the PWM mode selected n is the number of scan lines N is the number of cascaded TLC6946 devices tLSW is the line switching time 4 Table 4 3 shows the SCLK and GCLK minimum frequency requirement Table 4 3 SCLK and GCL...

Страница 40: ...2 DESIGN PARAMETER EXAMPLE VALUE RIREF red 4 27 kΩ IOUT MAX 6 mA RIREF green 10 7 kΩ IOUT MAX 2 4 mA RIREF blue 10 7 kΩ IOUT MAX 2 4 mA BC for red LED 5 mA 110 0110b BC for green LED 2 mA 110 0110b BC for blue LED 1 mA 0110 011b 4 1 2 FC Register Configuration 4 1 2 1 FC Register Data for Each Color According to the calculation in previous sections the function control registers could be configure...

Страница 41: ...signal after the last SCLK rising edge At the same time as the last SCLK falling edge the FC2 data is latched into the FC2 register The same as WRTFC1 there are 15 TLC6946 devices cascaded in this example and a total of 240 SCLK rising edges are required to shift the FC2 register data to all devices 4 WRTFC3 Shift the FC3 register data from SIN into the common shift registers of the devices with t...

Страница 42: ... after the 14 bits of GS data MSB in this design example as shown in Figure 4 2 b In this example there are 15 TLC6946 devices cascaded According to Equation 5 a total of 3840 bits of GS data must be sent for each GS data latch operation 2 Send the VSYNC command when all the 30 lines of GS data are latched into the internal display memory 3 Send the GCLK signal to start displaying the GS data just...

Страница 43: ...arameters DESIGN PARAMETER EXAMPLE VALUE VCC and VLED value 3 8 V SIN SOUT SCLK LAT and GCLK voltage range Low level GND TO 0 3 VCC high level 0 7 VCC to VCC Maximum current per LED IRED 5 mA IGREEN 2 mA IBLUE 1 mA PWM resolution 13 bits PWM mode 7 9 Display frames per second fFPS 60 Display refresh rate fVR 3840 Hz 4 2 1 1 System Structure To build an LED display board with 160 90 pixels 60 TLC69...

Страница 44: ...LSW 1 5 µs fGCLK 38 8 MHz Dual edge fGCLK B 19 4 MHz fSCLK 10 4 MHz 4 2 1 3 Channel Current and Brightness Control The same as described in Section 4 1 1 3 there are two methods to set the LED current This TLC6948 design takes method 2 as an example Table 4 12 Channel Current and Brightness Control Settings DESIGN PARAMETER EXAMPLE VALUE RIREF red 4 27 kΩ IOUT MAX 6 mA RIREF green 10 7 kΩ IOUT MAX...

Страница 45: ...ng edges to enable the write FC data function 2 WRTFC1 Shift the FC1 register data from SIN into the common shift registers of the devices with the SCLK rising edge Pull up the LAT signal before the last 5 SCLK rising edges and pull down the LAT signal after the last SCLK rising edge At the same time as the last SCLK falling edge the FC1 data is latched into the FC1 register In this example there ...

Страница 46: ... image display 4 2 3 1 Send GS Data to the TLC6948 Device Sending GS data to the TLC6948 device follows the procedure below Figure 4 4 13 bit GS Data for TLC6948 1 Shift the GS data from SIN into the common shift registers of the devices with the SCLK rising edge a The data length of each TLC6948 device is required to be 16 bits To meet this requirement add 3 0 value bits LSB after the 13 bit GS d...

Страница 47: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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