Inverting Gain Stages
3-3
EVM Applications
3.2
Inverting Gain Stages
Figure 3-3. DC-Coupled, Dual Power Supply, Inverting Gain Stage
VS-
-
+
U1
THS4601
7
4
VS+
J1
Vin-
Z1 0
R3
100
R1
61.9
Z5
100
2
3
6
TP3
Vout
Z3
49.9
R8
1 k
J3
Vout
Z2 0
R2
0
*Power supply decoupling is not shown
The Gain measured from J1 to J3 is 1, as determined by:
Vout
V
in
*
+ *
Z5
R3
The circuit provides approximately 50
Ω
of input impedance, as determined
by R1 || R3 (because R3 is at ground potential due to the action of the ideal
op amp model).
Figure 3-4. AC-Coupled, Single Power Supply, Inverting Gain Stage
-
U1
THS4601
2
7
VS+
J1
Vin-
Z1
R1
64.9
R3
100
Z5
100
R6
R7
R5
R2
0
Z2
J7
Vref
VS+
3
4
+
6
TP3
Vout
Z3
R8
1 k
J3
Vout
*Power supply decoupling is not shown
Z1 and Z3 are populated with dc-blocking capacitors, selected so they do not
interfere with the frequencies that are of interest. These capacitors create high
pass characteristics. R5 through R7 are selected to produce a dc potential on
the noninverting input equal, or close to VS+ divided by 2. The THS4601 has
low input bias currents, which allow larger bias setting resistors. If the user