Digital Audio Interfaces
8
SLAU809 – June 2019
Copyright © 2019, Texas Instruments Incorporated
TAS2110EVM User's Guide
Figure 7. Windows Playback device Sample Rate
9. Configure the device using the TAS2110 PPC3 Plug-in
6
Digital Audio Interfaces
Select the various digital audio interfaces on the TAS2110EVM through hardware settings and software
settings. Several headers on TAS2110 allow access to the following digital audio signals:
•
I2S Data out (SDOUT) from the TAS2110 (for example, current and voltage sense data)
•
I2S Data in (SDIN) to the TAS2110
•
I2S Word clock or frame sync (FSYNC)
•
I2S Bit clock (SBCLK)
•
I
2
C Clock (SCLK)
•
I
2
C Data (SDA)
To provide I2S data from an external source:
•
Remove jumpers J4, J3, and J5
•
Connect to SBCK, FSYNC, and SDIN by using pins 2-3 of Jumpers J4, J3, and J5
–
Signal is Pin 2
–
GND is Pin 3
•
SDOUT is available at a 1.8-V logic level through J14 or 3.3-V logic level through J12
•
I2S signals may operate at either 1.8-V or 3.3-V logic
