Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.27
LCDC: LIDD DMA Mode Issue
Revisions Affected
2.1, 2.0, 1.0
Details
After a DMA transfer is complete, the LIDD_DMA_EN bit in the LIDD_CTRL register is
driven low and the read/write pointers of the Asynchronous FIFO are designed to reset.
However, only the write pointer gets reset and, therefore, the FIFO sequence is corrupt.
This could cause flickering or tearing of images being displayed on an LCD.
Workarounds
After each DMA transfer, wait for Done interrupt by polling the DONE_RAW_SET bit in
the IRQSTATUS_RAW register, and then write 1 to the DMA_RST and LIDD_RST bits
in the CLKC_RESET register to perform software reset of the L3 and LIDD clock
domains. This returns the write and read FIFO pointers to their default values and allows
for proper FIFO operation.
This workaround has a side effect that needs to be considered. The LCDC drives the
LCD control signals to their active state when software reset is asserted if the active
states of the LCD panel inputs are opposite the LCDC default states. If this is the case, it
may be necessary to add a hardware isolation circuit to the LCD panel chip select signal
that disconnects the LCDC output from the LCD panel input before the software reset is
asserted. The LCDC output could be reconnected to the LCD panel input after LCDC
has been re-initialized. An example isolation circuit may be a single channel bus FET
switch inserted in the chip select signal path with the enable being controlled by a GPIO.
The LCD panel input would need a pull-up or pull-down resistor to force an inactive state
while the switch is open.
30
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
