Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 1.0.19
DDR3: Fully-Automated Hardware READ and WRITE Leveling Not Supported
Revisions Affected
2.1, 2.0, 1.0
Details
DDR3-based systems use a "fly-by" layout routing scheme where the address, clock,
and control signals are connected to multiple memory devices using a daisy-chain
topology, as opposed to DDR2-based systems which connect multiple devices using a
balanced T-topology. The "fly-by" routing scheme introduces skew in the arrival time of
the DDR signals to each memory device. DDR3 memories and DDR3 memory controller
provide hardware assisted training that optimizes timing for each data byte lane. This is
commonly referred to as READ and WRITE leveling. The objective of the READ and
WRITE leveling is to obtain correct values of the DLL ratios to compensate for the skew
and is done automatically during the initialization process.
The DDR3 controller does not reliably arrive at the optimal DLL ratios during the
automatic training process. Therefore, the automated hardware READ and WRITE
leveling is not supported.
Workarounds
Use the software-leveling procedure outlined below to obtain optimal DLL ratios that
compensate READ and WRITE timing:
1. Disable automated hardware READ and WRITE leveling by setting the
REG_RDWRLVL_EN bit in the RDWR_LVL_RMP_CTRL register to 0b.
2. Configure all EMIF4D registers, including AC timing values, as required for the
attached DDR3 memory device.
3. Determine the initial seed DLL ratio values to be used in the software-leveling
algorithm. These values are based on board trace lengths of DDR_CK(n) and
DDR_DQS(n).
4. Run the software-leveling algorithm with the initial seed DLL ratio values. The
algorithm iterates several times to find the optimum values for the given
configuration.
5. The software-leveling algorithm determines the optimum values for the following
registers in the DDR controller. Use the optimum values obtained from the program
when initializing the DDR controller.
•
DATA_PHY_RD_DQS_SLAVE_RATIO
•
DATA_PHY_FIFO_WE_SLAVE_RATIO
•
DATA_PHY_WR_DQS_SLAVE_RATIO
•
DATA_PHY_WR_DATA_SLAVE_RATIO
This procedure is only required once for a given combination of DDR3 memory devices,
DDR3 operating frequency, and printed circuit board layout. If there are any changes to
memory devices, operating frequency, or printed circuit board layout, the procedure
outlined above must be re-run.
23
SPRZ360F – October 2011 – Revised November 2013
Sitara™ AM335x ARM
®
Cortex™-A8 Microprocessors (MPUs) (Silicon
Revision 2.1, 2.0, 1.0)
Copyright © 2011–2013, Texas Instruments Incorporated
