8.15.4 Comparators
8.15.4.1 Low-Power Clocked Comparator
T
c
= 25 °C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage range
0
V
DDS
V
Clock frequency
SCLK_LF
Using internal DAC with VDDS as reference voltage,
DAC code = 0 - 255
0.024 - 2.865
V
Offset
Measured at V
DDS
/ 2, includes error from internal DAC
±5
mV
Decision time
Step from –50 mV to 50 mV
1
Clock
Cycle
(1)
The comparator can use an internal 8 bits DAC as its reference. The DAC output voltage range depends on the reference voltage
selected. See Section 8.15.2.1
8.15.4.2 Continuous Time Comparator
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
V
DDS
V
Offset
Measured at V
DDS
/ 2
±5
mV
Decision time
Step from –10 mV to 10 mV
0.78
µs
Current consumption
Internal reference
8.6
µA
(1)
The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using
the DAC
8.15.5 Current Source
8.15.5.1 Programmable Current Source
T
c
= 25 °C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Current source programmable output range (logarithmic
range)
0.25 - 20
µA
Resolution
0.25
µA
SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022
28
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