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13

NetU3_13

7

NetU3_7

3

NetU3_3

1

V PWR

19

C S_SOC KET

25

NetU3_25

11

NetU3_11

9

NetU3_9

5

DV DD_SOC

hole

hole

21

SDI

17

RBIA S _S O C

15

GND

27

NetU3_27

2

V PWR

1

NetC20_1

2

XFMR RETURN

23

NetU3_23

2

NetC20_1

1

GND

10

NetU3_10

4

GND

16

NetU3_16

22

SDO

26

V P_OTP_SO C

28

A V DD_SOC

1

GPIO2

1

LIN

1

RXD

1

GND

1

C S

1

OUTA

5

GND_UA RT

8

NetJ1_8

30

DA C _O UT

26

IO -A

24

IO -10 (S LO W O S C )

20

IO -9__RX

18

IO -7

12

IO -1

14

IO -3

6

GND

8

GND

4

GND

2

GND

14

NetU3_14

12

NetU3_12

8

NetU3_8

2

V REG_SOC

29

V _DV M_3

25

V _DV M_1

23

V _3.3_WO RLD

17

IO-6

19

V _5.0_WO RLD

13

IO-2

11

IO-0

3

IO-SC LK

7

IO-MOSI

5

IO-C S

1

IO-MISO

1

NetJP1_1

2

V PWR

1

GND

20

SC LK

18

NetU3_18

24

GND

1

V P_OTP_SO C

1

IN

1

TXD

1

XO UT

1

DV DD

1

V PWR

1

GND

1

LIM

1

C IN

1

GPIO1

1

XIN

1

V REG

1

V _LIN

1

GND

1

LIN

1

V _LIN

1

GND

1

RBIA S

1

SDI

1

O UTB

1

V REF

1

GND

2

P WR-IN

1

GND

1

GND_UA RT

1

5V

1

GND

1

NetJP4_2

2

V REG

3

OUTB

1

V REG

2

NetJP4_2

1

OUTA

2

NetJP4_2

1

RX_232

1

TX_232

6

NetC20_1

4

GND

5

NA_

4

NetJ1_4

2

TX_232

1

NetJ1_1

1

GND

9

NetJ1_9

6

NetJ1_6

28

IO -B

22

P WR-DWN

16

IO -5

6

NetU3_6

10

IO-8__TX

27

V _DV M_2

15

IO-4

21

IO-OSC

0

9

IO-11

1

XF MR RETURN

1

GND

2

NetC20_1

3

RX_232

7

NetJ1_7

1

S C LK

1

V P _O TP

1

TES TO _A

1

TES TO _D

1

S DO

1

GND

1

A V DD

1

V P WR

1

GND

1

NetC26_1

11

NetJ1_11

10

NetJ1_10

1

P WR-IN

0

0

1

GND

1

GND

1

IO -9__RX

2

LIN RXD

1

IO -8__TX

2

LIN TXD

1

C S_SO C KET

2

IO-11

1

SDI

2

IO-MOSI

1

C S

2

IO-C S

1

SDO

2

IO-MISO

1

LIN EN

2

IO-0

1

SC LK

2

IO-SCLK

6

NetC25_2

7

NetC24_1

8

RX_232

9

RXD

10

~INVALID

11

TXD

2

NetC25_2

3

NetC22_1

4

NetC23_2

5

NetC25_1

12

GND_UART

13

TX_232

14

GND_UART

1

GND_UART

16

NetC26_1

1

NetC20_1

2

GND

2

LIM

3

NWAKE

2

LIN EN

15

GND

14

LIM

17

RBIA S

18

TESTO _D

12

C IN

11

TXD

20

SC LK

21

SDI

22

SDO

9

GP IO 2

8

GP IO 1

7

XO UT

23

O UTB

24

GND

25

O UTA

6

XIN

5

DV DD

4

GND

27

V REF

28

A V DD

2

V REG

1

V P WR

6

LIN

7

V _LIN

4

LIN TXD

1

LIN RXD

16

TESTO _A

19
C S

13
IN

10

RXD

26

V P _O TP

3

LIN

5

GND

8

NetU1_8

1

NetJP4_2

2

V REG

3

OUTB

2

NetC23_1

15

NetC26_1

1

NetC25_1

4

GND

5

NA_

6

NetC20_1

1

VPWR

1

XFMR RETURN

1

NetC26_1

2

GND_UART

2

GND

13

NetU3_13

7

NetU3_7

3

NetU3_3

1

VPWR

19

CS_SOCKET

25

NetU3_25

9

NetU3_9

11

NetU3_11

5

DVDD_SOC

hole

ho le

15

GND

17

RBIAS_SOC

21

SDI

27

NetU3_27

2

VPWR

1

NetC20_1

2

XFMR RETURN

23

NetU3_23

2

NetC20_1

1

GND

10

NetU3_10

4

GND

16

NetU3_16

22

SDO

26

VP_OTP_SOC

28

AVDD_SOC

1

GPIO2

1

LIN

1

RXD

1

GND

1

CS

1

OUTA

5

GND_UART

8

NetJ1_8

30

DAC_OUT

24

IO-10 (SLOW OSC)

26

IO-A

18

IO-7

20

IO-9__RX

14

IO-3

12

IO-1

4

GND

8

GND

6

GND

2

GND

8

NetU3_8

12

NetU3_12

14

NetU3_14

2

VREG_SOC

29

V_DVM_3

23

V_3.3_WORLD

25

V_DVM_1

19

V_5.0_WORLD

17

IO-6

11

IO-0

13

IO-2

5

IO-CS

7

IO-MOSI

3

IO-SCLK

1

IO-MISO

2

VPWR

1

NetJP1_1

1

GND

18

NetU3_18

20

SCLK

24

GND

1

VP_OTP_SOC

1

IN

1

XOUT

1

TXD

1

VPWR

1

DVDD

1

GND

1

LIM

1

GPIO1

1

CIN

1

VREG

1

XIN

1

V_LIN

1

GND

1

V_LIN

1

LIN

1

GND

1

SDI

1

RBIAS

1

VREF

1

OUTB

1

GND

2

PWR-IN

1

GND

1

GND_UART

1

5V

1

GND

3

OUTB

2

VREG

1

NetJP4_2

2

NetJP4_2

1

VREG

2

NetJP4_2

1

OUTA

1

TX_232

1

RX_232

5

NA_

4

GND

6

NetC20_1

4

NetJ1_4

1

NetJ1_1

2

TX_232

1

GND

9

NetJ1_9

6

NetJ1_6

16

IO-5

22

PWR-DWN

28

IO-B

6

NetU3_6

10

IO-8__TX

21

IO-OSC

15

IO-4

27

V_DVM_2

0

9

IO-11

1

XFMR RETURN

1

GND

2

NetC20_1

3

RX_232

7

NetJ1_7

1

SCLK

1

VP_OTP

1

TESTO_A

1

SDO

1

TESTO_D

1

AVDD

1

GND

1

VPWR

1

GND

11

NetJ1_11

1

NetC26_1

10

NetJ1_10

1

PWR-IN

1

GND

0

0

1

GND

1

5V

2

VPWR

1

XIN

1

VREG

2

GND

2

NetC26_1

2

GND

1

VREG_SOC

1

VPWR

2

GND

1

DVDD_SOC

2

VP_OTP

2

GND

2

GND

1

RBIAS_SOC

1

AVDD_SOC

2

GND

1

VP_OTP_SOC

1

NetD3_1

2

V_LIN

1

XOUT

1

VREG

2

GND

2

5V

1

TXD

2

GND_UART

1

NetC24_1

1

GND_UART

2

NetC23_2

2

GND_UART

1

NetC22_1

1

NetC23_1

1

5V

1

LIN

2

V_5.0_WORLD

1

PWR-DWN

1

NetD3_1

2

GND

2

GND

1

DVDD

2

GND

2

GND_UART

1

NetC26_1

2

GND_UART

1

NetC26_1

2

GND

1

VP_OTP_SOC

1

VP_OTP_SOC

2

GND

3

XOUT

2

GND

1

NWAKE

2

LIN EN

1

5V

2

LIN RXD

1

5V

2

LIN

2

GND

2

GND

1

CIN

2

LIM

1

IN

2

GND

1

RBIAS

2

GND

1

AVDD

2

GND

1

VPWR

2

GND

2

GND

1

V_LIN

1

VPWR

2

PWR-IN

1

XIN

4

NetX1_4

2

GND

1

VPWR

2

GND

1

VREG

2

GND

2

VP_OTP_SOC

1

VP_OTP_SOC

1

NetJP1_1

2

NetX1_2

1

VP_OTP

2

GND

www.ti.com

PGA450Q1EVM Schematics and Layout Drawings

25

SLDU007C – March 2012 – Revised November 2015

Submit Documentation Feedback

Copyright © 2012–2015, Texas Instruments Incorporated

PGA450Q1EVM User’s Guide

Figure 23. PCB Layout, Bottom

Figure 24. PCB Layout, Top

Содержание PGA450Q1EVM

Страница 1: ...cket for Programming OTP 6 6 Transformer and Transducer 6 7 PGA450 Q1 Communication Interfaces 7 7 1 SPI 7 7 2 LIN 7 7 3 UART 8 8 Controlling the PGA450 Q1 Memory Spaces With the GUI 9 8 1 Using the Register Grids to Manipulate the Register Spaces 9 8 2 ESFR Registers 10 8 3 EEPROM Registers 10 8 4 RAM 10 8 5 OTP 10 8 6 DEVRAM 13 8 7 FIFO ECHO 14 9 LIN Master 16 10 Keil uVision Settings for Progra...

Страница 2: ...nge of transducers with frequency ranges from 40 kHz to 70 kHz The PGA450 Q1 device incorporates an analog front end AFE and a 8051W microprocessor core The AFE includes voltage regulators an amplifier an ADC an oscillator and a temperature sensor The PGA450 Q1 device also implements a LIN 2 1 physical layer for communication For more details see the device data sheet 2 EVM Overview The features o...

Страница 3: ...www ti com EVM Overview 3 SLDU007C March 2012 Revised November 2015 Submit Documentation Feedback Copyright 2012 2015 Texas Instruments Incorporated PGA450Q1EVM User s Guide put in the reset state ...

Страница 4: ...use the screw terminal P2 3 2 Controlling and Powering the PGA450Q1EVM via the USB Interface Board The PGA450Q1EVM is shipped with a USB interface board that provides a link from the PC controlled GUI described later to the EVM Connect the USB interface board to the PGA450 Q1 device by connecting the 30 pin female header on the interface board to P6 the male 30 pin header on the PGA450Q1EVM The TI...

Страница 5: ...he transformer primary top terminal is connected to the VREG pin on the PGA450 Q1 device for single ended configuration Open The transformer primary top terminal is not connected to the VREG pin on the PGA450 Q1 device 4 2 Default Jumper Settings 1 Ensure the TI GER USB Interface board has no jumpers populated except for the 5 V digital I O level option located adjacent to the red 5 V test point T...

Страница 6: ...d XDCR If XDCR is Murata MA58MF14 7N 2000 pF capacitance is installed and 1500 pF capacitance is provided as an alternative If XDCR is Murata MA58AF14 0N 1500 pF capacitance is installed Alternative specifications include 1500 pF 0805 250 V 20 NPO Figure 2 Transformer and Connector for the Transducer A matched transformer transducer pair is included on the PGA450Q1EVM Table 4 lists closed top tran...

Страница 7: ...tapped to double the voltage Typically a tuning capacitor is needed to match the resonant frequency between the transducer and transformer 1 CPT RT LT and CT are characteristics of the transducer LSEC is the secondary inductance of the transformer and CTUNE is an external capacitor placed across the terminals of the transducer Figure 3 Equivalent Circuit of Transformer Transducer Sensor Pair 7 PGA...

Страница 8: ...2 C26 100uF SMT 35V 20 AL GND_UART GND_UART GND_UART tssop footprint and P N TXD R11 10 0k 0603 1 10W 5 5V PGA450 Q1 Communication Interfaces www ti com 8 SLDU007C March 2012 Revised November 2015 Submit Documentation Feedback Copyright 2012 2015 Texas Instruments Incorporated PGA450Q1EVM User s Guide 7 3 UART An RS 232 transceiver MAX3221 is present on the EVM that can be used as a debugging inte...

Страница 9: ...unctions is in one of the following sections 8 1 1 ZERO GRID The ZERO GRID button replaces the contents of the entire grid with 0 8 1 2 DESELECT GRID The DESELECT GRID button removes any selections that have been made in the grid without performing any operations on the registers that were selected 8 1 3 SAVE GRID The SAVE GRID button takes the contents of the register grid and saves them to a TXT...

Страница 10: ...updated on the GUI by clicking on the READ SELECTED or READ ALL button 8 4 RAM The RAM tab is set up only for individual register read writes without the use of the grid When this tab is displayed the READ SELECTED READ ALL and WRITE SELECTED WRITE ALL buttons perform the same operations respectively The PGA450 Q1 device has 512 bytes of general purpose RAM This general purpose RAM is memory mappe...

Страница 11: ... the contents of a HEX file into the GUI RAM for use with other operations When the button is pressed a second window opens that allows the user to locate and open the desired HEX file on the PC See Figure 6 for an example of this operation Figure 6 Loading a HEX File Into the GUI 8 5 2 Program OTP Memory from HEX File If the Program OTP Memory from HEX File check box was checked default when the ...

Страница 12: ...he HEX file If the OTP memory matches the contents of the HEX file the GUI displays the message OTP Memory Verification Successful as seen in Figure 7 Figure 7 OTP Memory Successful Programming Verification 8 5 4 Check OTP Status Press the Check OTP Status button to verify what is currently programmed into OTP The three possible results are Programmed to Jump to DEVRAM The jump to DEVRAM statement...

Страница 13: ...8051 program file into the 8051 MCU in the PGA450 Q1 device The process of loading the HEX file into the DEVRAM is identical to that of OTP For a pristine IC that has never been programmed OTP Status reads OTP Empty in order to run software from DEVRAM the OTP memory must be programmed with some specific instructions to redirect the 8051 µP to DEVRAM This must only be done once To do this check th...

Страница 14: ...contents can be displayed on the GUI and plotted in Excel by clicking the Read and Save FIFO Data to File button NOTE Note Microsoft Office version 2007 or above is required for this function to work properly Figure 9 Echo Data Stored in FIFO RAM Plotted in Excel 8 7 2 EVAL Monitor This tab graphs the output of the digital data path directly in the GUI The 8051W microcontroller must be in reset to...

Страница 15: ...options reduce the number of data points plotted which results in faster plotting 8 7 2 4 Clear Plot The CLR button clears all data from the graph If the Clear Plot option is checked echo data will be cleared from the plot every loop If Clear Plot is not checked every loop will plot the new echo data in a new color on top of the existing data on the graph 8 7 2 5 Export Data to Excel This option e...

Страница 16: ... before the PID is transmitted to the slave 2 Enter 0 8 bytes of data in the Data to be Txed box Each data byte must be entered in Hex 3 Select the CLASSIC or ENHANCED checksum which must match the LIN checksum setting in the PGA450 Q1 ESFR LIN_CFG register 4 Click on the TRANSMIT button In order to receive data from PGA450 Q1 device using a LIN frame the user must do the following 1 Enter the Fra...

Страница 17: ... a current license the product runs as a lite or evaluation edition with a few limitations 10 2 Setup Figure 11 DEVRAM Target Options To Program to DEVRAM 1 Change the code range to the DEVRAM memory space a Right click on Target 1 in the project window and select Options for Target b Go to the BL51 Locate tab and modify the Code Range to go from 0x2000 0x3FFF 2 Copy the following to the Code box ...

Страница 18: ...ct window and select Options for Target b Go to the BL51 Locate tab and modify the Code Range to go from 0x0000 0x1FFF 2 Delete everything in the Code box 3 Comment out the DEVRAM section in STARTUP A51 and uncomment the OTP section a An example of this is shown in Figure 14 Figure 13 DEVRAM STARTUP A51 Example Figure 14 OTP STARTUP A51 Example Instructions Build the PGA450 uvproj to generate the ...

Страница 19: ...efficient clock selection FIFO mode and FIFO downsample size 1 Make sure all jumpers are connected according to the default settings see Section 4 2 2 Connect the hardware and power supply see Section 3 Make sure USB cable is connected to the computer and the interface board It is recommended to monitor power supply current Normal idle current is around 6 mA Active current is around 15 mA 3 Launch...

Страница 20: ...w users to quickly observe the echo signal as an amplified analog signal or from a DAC output which converts a digitally filtered echo signal In the Evaluation tab quick access buttons Amplifier Output unfiltered and Datapath Output filtered are available The signal is viewable on the DACO pin Only one mode can be selected at a time See Figure 16 and Figure 17 for the captured waveforms Figure 16 ...

Страница 21: ...SLDU007C March 2012 Revised November 2015 Submit Documentation Feedback Copyright 2012 2015 Texas Instruments Incorporated PGA450Q1EVM User s Guide Figure 17 DAC Output of Filtered Signal Channel 2 and Drive Voltage Channel 1 ...

Страница 22: ...1AQDRQ1 RXD 1 EN 2 NWAKE 3 TXD 4 GND 5 LIN 6 VSUP 7 INH 8 U1 LIN TxD GND LIN RxD GND V_LIN V_LIN GND LIN EN FOOTPRINT OK 4 21 10 BAV3004W 7 F D3 R5 1 0k 0603 1 10W 5 C5 220pF 0603 50V 10 X7R R4 1 0k 0603 1 10W 5 C4 0 1uF 0805 50V 10 X7R R3 0 0603 1 10W 5 NWAKE R6 0 0603 1 10W 5 GND 5V 5V V_LIN LIN GND GND LIN PGA450Q1EVM Schematics and Layout Drawings www ti com 22 SLDU007C March 2012 Revised Nove...

Страница 23: ... 1 FORCEON 12 GND 14 V 3 V 7 TOUT RS232 13 RIN RS232 8 VCC 15 FORCEOFF 16 INVALID 10 U4 1 2 3 4 5 6 7 8 9 11 10 J1 D Connector 9 C23 0 1uF 0603 50V 10 X7R C25 0 47uF 0805 50V 10 X7R C28 0 1uF 0603 50V 10 X7R GND GND_UART TX_232 RX_232 INVALID C22 0 47uF 0805 50V 10 X7R C24 0 47uF 0805 50V 10 X7R TX_232 5V RS232 VCC Rx Tx C27 1uF 0603 25V 10 X7R R13 0 0603 1 8W 5 L1 BEAD GND_UART GND_UART GND_UART ...

Страница 24: ...ppm C RBIAS GND GND C6 0 1uF 0603 50V 10 X7R VPWR VREG_SOC DVDD_SOC VP_OTP _SOCAVDD_SOC C7 0 1uF 0603 50V 10 X7R C8 0 1uF 0603 50V 10 X7R C9 0 1uF 0603 50V 10 X7R C10 0 1uF 0603 50V 10 X7R GND GND GND GND XIN XOUT NX3225SA 16 000000MHZ 1 3 4 2 X1 16MHz 15ppm 8pF C17 12pF 0603 100V 5 NPO C18 12pF 0603 100V 5 NPO GND GND 1 6 3 4 2 TI to supply TR1 TRANSFO RMER XFMR RETURN VREG GND OUTB OUTA C21 100u...

Страница 25: ...3_13 7 NetU3_7 3 NetU3_3 1 VPWR 19 CS_SOCKET 25 NetU3_25 9 NetU3_9 11 NetU3_11 5 DVDD_SOC hole hole 15 GND 17 RBIAS_SOC 21 SDI 27 NetU3_27 2 VPWR 1 NetC20_1 2 XFMR RETURN 23 NetU3_23 2 NetC20_1 1 GND 10 NetU3_10 4 GND 16 NetU3_16 22 SDO 26 VP_OTP_SOC 28 AVDD_SOC 1 GPIO2 1 LIN 1 RXD 1 GND 1 CS 1 OUTA 5 GND_UART 8 NetJ1_8 30 DAC_OUT 24 IO 10 SLOW OSC 26 IO A 18 IO 7 20 IO 9__RX 14 IO 3 12 IO 1 4 GND...

Страница 26: ...isions may differ from page numbers in the current version Changes from B Revision June 2015 to C Revision Page Changed the Transformer and Connector for the Transducer schematic 6 Changed the Murata part numbers for the transducer in the Transformer and Transducer section 6 Added Murata note on availability of ultrasonic sensors 7 Changed the Schematic PGA450 Q1 TPIC8500 Q1 24 Changed the PCB Lay...

Страница 27: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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