Texas Instruments OMAP36 Series, Техническое справочное руководство

Страница: 795 / 3738

Public Version
www.ti.com
IVA2.2 Subsystem Basic Programming Model
NOTE: Because of the pipelined nature of the VBUS interface, the DSP megamodule module can
have multiple DMA transfers in flight at a time. To avoid priority inversion, the DSP
megamodule must not only evaluate the priority of the transfer at the head of the EMC
queue(s), but the priority of all transfers that have been accepted/queued on the VBUS
interface(s), and of higher priority transfers that are queued in the device-level DMA
infrastructure.
• MDMAARBE register - Master DMA priority programming model
The IVA_IDMA. MDMAARBE [18:16] PRI field controls the submission priority for master DMA
transactions (which are a result of cache misses or long-distance accesses to nonconfiguration space)
and configuration bus transactions (long-distance accesses to configuration space or IDMA transfers to
configuration space).
The IVA_IDMA.
MDMAARBE priority is different from other programmable priorities in the system, in
that the priority value does not affect internal arbitration for resources. This PRI[3:0] value is simply
used as the VBUS priority value for all transactions initiated by the DMA master interface or
memory-mapped register configuration interface.
Arbitration for the internal half of the transfer depends on the initiator (which could be DSP CPU, PMC,
or DMC) or user coherence (UMC), or IDMA, etc. Arbitration for the external half of the transfer is
DMA-dependent, and should rely on the Vbus priority, which is copied from the
IVA_IDMA.
MDMAARBE [18:16] PRI field.
NOTE: Because no internal arbitration results from the IVA_IDMA. MDMAARBE register, there is no
need for the MAXWAIT field in this register.
5.4.9.3 SL2 Memory Management
5.4.9.3.1 SL2 Performance Optimizations
To limit the number of accesses through the SL2 interface and to optimize bandwidth, it is recommended
that the user access SL2 using, as much as possible, bursts and aligned on burst boundaries. Optimum
bandwidth savings can be obtained by doing bursts of 8x32 aligned on 32-byte boundaries.
This can be done using ARM968 (sequencer module) LDM or STM instructions. For details, see the ARM
reference manual.
5.4.9.3.2 SL2 Performance Limitations
Accesses through the SL2IF OCP interface to SL2 memory are not intended to be optimized for single
reads, but only for bursts. Maximum bandwidth can be obtained using bursts of 8x32b bursts or larger
(bursts larger than 8x32 are divided into 8x32 bursts). Generating single requests to the SL2IF interface
has two disadvantages:
•
Uses a large portion of the SL2 bandwidth, resulting in iME and iLF performance degradation
• Increases dynamic power consumption
In particular, ARM968 instruction fetches generate single requests on the local interconnect. SL2 is not
optimized for ARM968 instruction direct fetching. If the ITCM is too small for an ARM968 program, an
ARM968 program must be DMAed in from memory (possibly SL2, as DMA accesses are bursted).
5.4.9.3.3 SL2 Illegal Accesses
It is illegal for the user to generate unaligned bursts that span SL2 address range boundaries.
795 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated