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IVA2.2 Subsystem Basic Programming Model
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NOTE: CPU priority is software-programmable, but it is considered static (1-time-programmable) for
bandwidth management. That is, during normal operation, all DSP CPU transactions are of
the same priority. There is no concept of priority inheritance for CPU-initiated transfers as a
result of CPU transfer A set at priority X and CPU transfer B set at priority Y. Because
CPUARB must be programmed by the CPU, and is therefore a run-time programmation, the
effect of the new CPUARB value must take effect for future CPU transfers.
• UCARB registers - User coherence operations
User coherence operations are broken into two types, block-oriented coherence and global coherence
operations. The priority of these requests relative to other requests in the system varies as follows:
– Global user coherence: Always highest priority
– Block-oriented coherence: Always lowest priority
Because user coherence priority is fixed, the UCARB registers do not include a priority field. And because
global user coherence operations are inherently highest priority, the MAXWAIT field programming applies
only to block-oriented user coherence operations, not to global cache operations.
The UCARB[5:0] MAXWAIT field affects only the UMC (IVA_UMC. UCARBU register) and the DMC
(IVA_DMC. UCARBD register). The priority values (being fixed) are assumed to be known at both the UMC
and the DMC.
NOTE: The UCARB[5:0] MAXWAIT field (and the implied priorities) does not control the priority of
coherence operations that result from DMA transactions or CPU transactions.
• IDMAARB registers - IDMA priority programming model
IDMA supports two active transfers at any time through IDMA channel 0 (used for memory to/from
configuration bus transfers) and IDMA channel 1 (used for memory-to-memory transfers). The
IDMAARB[5:0]MAXWAIT field is used to determine the maximum wait time for IDMA transactions. The
priority level is not programmed through the IDMAARB register. Instead, the priority level is
programmed directly through the IDMA control registers. In summary, IDMA transfer priority is:
– IDMA channel 0: Always highest priority
– IDMA channel 1: Programmable priority: the IVA_IDMA. IDMA1_COUNT [31:29] PRI field
For this reason, the IDMAARB registers do not include a priority field. The IDMAARB[5:0] MAXWAIT
field affects not only the EMC (IVA_IDMA.
IDMAARBE register) but also the UMC
(IVA_UMC. IDMAARBU register) and the DMC (IVA_DMC. IDMAARBD register).
NOTE: IDMA channel 0 has no need for priority inheritance, because it is always the highest priority
transfer in the system.
However, if an IDMA channel 1 transfer and an IDMA channel 0 transfer are pending at the
same instant, but the IDMA channel 1 queue is blocked because of contention with another
requestor, the IDMA channel 1 transfer should briefly inherit the priority of the IDMA channel
0 transfer (which is always 0x0) so that the pending dataphase on IDMA channel 1 can
complete and the normal priority mechanism can take control.
• SDMAARB registers - Slave DMA priority programming model
The DSP megamodule slave DMA (SDMA) interface can support multiple active transfers at a time. The
SDMAARB[5:0] MAXWAIT field controls the maximum wait time for all slave DMA transactions. The
priority level is not programmed by the SDMAARB register. Instead, the priority level is dictated by the
priority fields of the IVA_TPCC.QUEPRI register.
The SDMAARB[5:0] MAXWAIT field does not affect only the EMC (IVA_IDMA. SDMAARBE register), but
also the UMC (IVA_UMC. SDMAARBU register) and the DMC (IVA_DMC. SDMAARBD register).
794 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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