Texas Instruments OMAP36 Series, Техническое справочное руководство

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PRCM Use Cases and Tips
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switching, because OPP130 has a higher frequency.
The SmartReflex1 and voltage processor1 modules are disabled for voltage scaling.
SR1. SRCONFIG [11] SR_EN 0x0 Disable the SmartReflex1 module.
PRCM. PRM_VP1_CONFIG [0] VPENABLE 0x0 Disable the voltage processor1 module.
The parameters of the SmartReflex1 error generator are configured corresponding to OPP130.
SR1. NVALUERECIPROCAL [23:20] SENPGAIN Configured according to the settings in eFuse
SR1. NVALUERECIPROCAL [19:16] SENNGAIN See Section 3.5.6.5.4.5 , Parameter Configuration.
SR1. NVALUERECIPROCAL [15:8] RNSENP
SR1. NVALUERECIPROCAL [7:0] RNSENN
SR1. SRCONFIG [9] ERRORGENERATORENABLE 0x1 Enable the error generator.
The OPP change-done interrupt of the voltage processor1 and the voltage processor bounds interrupt
of the SmartReflex1 module are enabled. The remaining interrupts of the voltage processor1 and
SmartReflex1 modules can be masked.
SR1. ERRCONFIG [22] VPBOUNDSINTENABLE 0x1 Enable the SmartReflex1 voltage processor interrupt.
PRCM. PRM_IRQENABLE_MPU 0x1 Enable the VP1 OPP change-done interrupt.
VP1_OPPCHANGEDONE_EN
The voltage processor1 and SmartReflex1 modules are enabled.
PRCM. PRM_VP1_CONFIG [0] VPENABLE 0x1 Enable the voltage processor1 module.
SR1. SRCONFIG [11] SR_EN 0x1 Enable the SmartReflex1 module.
The SmartReflex1 module sends the OPP change-done interrupt when the OPP change is complete
and the voltage is stable.
PRCM. PRM_IRQSTATUS_MPU [10] VP1_ Read On read, if this bit is 0x1, the OPP change is complete.
OPPCHANGEDONE_ST
PRCM. PRM_IRQSTATUS_MPU [10] VP1_ 0x1 Writing 0x1 clears the Interrupt status bit.
OPPCHANGEDONE_ST
Enable the voltage processor1 interrupt for automatic SmartReflex1 operation.
SR1. ERRCONFIG [22] VPBOUNDSINTENABLE 0x1 Enable the voltage processor bounds interrupt.
After voltage switching is complete, the processor frequencies must be switched. The DPLL1 and
DPLL2 frequencies are scaled by changing the multiplier and divider values. The DPLLs must relock
and switch to bypass mode.
DPLL frequency (F
DPLL
) is calculated as:
F
DPLL
= (SYS_CLK*2*M)/(N+1)
If SYS_CLK is 38.4 MHz, the values of M and N can be set as:
PRCM. CM_CLKSEL1_PLL_MPU [18:8] MPU_DPLL_MULT - The multiplier and divider of DPLL1 are configured for
OPP130 frequency.
PRCM. CM_CLKSEL1_PLL_MPU [6:0] MPU_DPLL_DIV -
PRCM. CM_CLKSEL1_PLL_IVA2 [18:8] IVA2_DPLL_MULT - The multiplier and divider of DPLL2 are configured for
OPP130 frequency.
PRCM. CM_CLKSEL1_PLL_IVA2 [6:0] IVA2_DPLL_DIV -
3.7.1.3.3 Switch VDD2 OPPs
1. Switch from VDD2 OPP100 to VDD2 OPP50, assuming that
• OPP100 (VDD2 = v3 , (DPLL3_CLKOUT = f
dpll3
3, CORE_CLK = f
core
3))
• OPP50 (VDD2 = v2 , (DPLL3_CLKOUT = f
dpll3
2, CORE_CLK = f
core
2))
and v3 > v2 , f
dpll3
3 > f
dpll3
2 , f
core
3 > f
core
2.
To switch from OPP100 to OPP50, the DPLL3 output divider must be configured to divide the output
by 2. Frequency switching must be done before voltage switching.
454 Power, Reset, and Clock Management SWPU177N – December 2009 – Revised November 2010
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