MPU INTC
ARM host processor
If FIQs are enabled(F==0):
Finish the current instruction number N
Store address of next instruction to be executed in the
Link Register (R14)
Save CPSR before execution in the SPSR
Enter ARM FIQ mode
Execute interrupt vector
Device peripheral module
M_IRQ_n
asserted
asserted
Save ARM critical context
Save the INTC priority threshold
Identify interrupt source
Get the active IRQ priority
Set the IRQ priority to the priority threshold
Allow a new IRQ and FIQ at INTC side by setting
to 1 the NEWIRQAGR and NEWFIQAGR bit
.
Jump to revelant interrupt subroutine handler
Handles the event (functional procedure)
Deassert the interrupt M_IRQ_n at device
peripheral module side.
Restore the INTC priority threshold
Restore ARM critical context
Branch
ARM host processor
Restore the whole CPSR
Restore the PC
Branch
Branch
Return
Main Program
Execution of the instruction number 1
Execution of the instruction number N
Step 1
Step 2
Main Program
Execution of the instruction number N+1
Return
Software
Hardware
intc-006
If the IRQ_n is not masked and configured as an IRQ/FIQ,
the MPU_INTC_IRQ/MPU_INT_FIQ line is asserted
MPU _INTC_IRQ/
MPU _INTC_FIQ
Disable IRQs and FIQs at ARM side
ISR in IRQ/FIQ mode
Revelant subroutine handler in IRQ/FIQ mode
Disable IRQ/FIQ at ARM side
Enable IRQ/FIQ at ARM side
ISR in IRQ/FIQ mode
Public Version
Interrupt Controller Basic Programming Model
www.ti.com
Figure 12-6. Nested IRQ/FIQ Sequence
NOTE:
The differences between the IRQ and the FIQ sequence are highlighted in blue and bold
characters.
2420
Interrupt Controller
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
Содержание OMAP36 Series
Страница 174: ...174 List of Tables SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 692: ...692 MPU Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1084: ...1084 IVA2 2 Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 1990: ...1990 2D 3D Graphics Accelerator SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2334: ...2334 Memory Subsystem SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2700: ...2700 Memory Management Units SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2868: ...2868 HDQ 1 Wire SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 2974: ...2974 UART IrDA CIR SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3054: ...3054 Multichannel SPI SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3462: ...3462 MMC SD SDIO Card Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3508: ...3508 General Purpose Interface SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3584: ...3584 Initialization SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...
Страница 3648: ...3648 Debug and Emulation SWPU177N December 2009 Revised November 2010 Copyright 2009 2010 Texas Instruments Incorporated ...