Texas Instruments OMAP36 Series, Техническое справочное руководство

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SDRAM Controller (SDRC) Subsystem
Table 10-165. SDRC_ERR_TYPE
Address Offset 0x0000 004C
Physical Address 0x6D00 004C Instance SDRC
Description This register provides additional information about the last illegal access.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESERVED
ERRORADD ERRORDPD
ERRORVALID
ERRORMCMD
ERRORCONNID
Bits Field Name Description Type Reset
31:12 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x00000
11:8 ERRORCONNID Identifies the interconnect ConnID of the illegal access initiator: Refer to RW 0x0
the top level documentation of the device using the SDRC module.
7 RESERVED Write 0 for future compatibility. Read returns 0. RW 0x0
6:4 ERRORMCMD System command of the transaction that caused the error (3-bit field) RW 0x0
3:2 ERRORADD Flag that indicates access is to an illegal address RW 0x2
Read 0x0: The system request was to an address outside the memory
space.
Write 0x0: Clear ErrorAdd bit field.
Read 0x1: The system request was to an address outside the register
space.
Write 0x1: No effect
Read 0x2: No Err Add. Not an address error
Write 0x2: No effect
Read 0x3: No Err Add. Not an address error
Write 0x3: No effect
1 ERRORDPD Transaction error while the memory is in deep-power-down mode RW 0x0
Read 0x0: The memory was not in deep-power-down mode when the
error occurred.
Write 0x0: No effect
Read 0x1: The error is due to an unexpected access while the memory
was in deep-power-down mode.
Write 0x1: Clear the ErrorDPD bit field.
0 ERRORVALID Error validity status - Must be explicitly cleared with a write 0 transaction. RW 0x0
Read 0x0: All error fields no longer valid
Write 0x0: Clear ErrorValid bit field
Read 0x1: Error detected and logged in the other error fields
Write 0x1: No effect
Table 10-166. Register Call Summary for Register SDRC_ERR_TYPE
SDRAM Controller (SDRC) Subsystem
• Error Management : [0] [1] [2] [3] [4]
• SDRC Register Summary : [5]
2319 SWPU177N – December 2009 – Revised November 2010 Memory Subsystem
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