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Display Subsystem Register Manual
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Bits Field Name Description Type Reset
5 TRIGGER_RESET Send the reset trigger to the peripheral. RW 0x0
0x0: READS: Reset trigger generation is completed. It is reset by
HW when it is completed.
WRITES: Cancellation of the request for Reset trigger generation
(maybe too late since it is already on going)
0x1: READS: Generation of the reset trigger has been requested by
user (could be on going but not completed yet).
WRITES: Request for Reset trigger to be sent to the peripheral.
4 VP_CLK_RATIO This bit indicates the clock ratio between VP_CLK and VP_PCLK. RW 0x0
The clock VP_PCLK is generated from VP_CLK. It is divided down.
The information is only used when the video port is used to provide
data in command mode. In the case of video mode, it is not used.
0x0: The clock VP_PCLK is the clock VP_CLK divided by 2. The
duty cycle of VP_PCLK is 50/50.
0x1: The clock VP_PCLK is the clock VP_CLK divided by 3 or more.
The duty cycle of VP_PCLK is not 50/50 for odd ratio numbers
(3,5,7,...).
3 TX_FIFO_ Defines the arbitration scheme for granting the VC pending ready RW 0x0
ARBITRATION requests in the TX FIFO
0x0: Round-Robin Scheme is used
0x1: Sequential Scheme is used
2 ECC_RX_EN Enables the ECC check for the received header (short and long RW 0x0
packets for all VC IDs).
0x0: Disabled
0x1: Enabled
1 CS_RX_EN Enables the checksum check for the received payload (long packet RW 0x0
only for all VC IDs).
0x0: Disabled
0x1: Enabled
0 IF_EN Enables the module. When the module is disabled the signals from RW 0x0
the complex I/O are gated (no updates of the interrupt status
register).
It is not possible to change the bit fields in the
DSI_CTRL register,
except IF_EN when it is enabled. All the other registers can be
changed except the ones that require
DSI_VCn_CTRL [0] VC_EN to
be equal to 0 to be modified.
0x0: The interface is disabled. If one of the VC uses the video mode
with the video port to receive the data, the DSI protocol engines is
disabled when the next VSYNC is received and all the data in the
FIFO for the other VCs in command mode are sent to the
peripherals (if BTA_EN bit is enabled, the DSI protocol engine needs
to wait for the response and BTA from the peripheral before
disabling all the internal logic since an acknowledge is requested).
0x1: The interface is enabled immediately, the data acquisition on
the video port starts on the next VSYNC (video mode) or first data
received in the Slave port FIFO (command mode).
Table 7-379. Register Call Summary for Register DSI_CTRL
Display Subsystem Environment
• Data/Clock Configuration : [0] [1] [2]
• Video Port (VP) Interface : [3] [4] [5] [6]
• Video Port Used for Video Mode : [7] [8] [9]
• Video Port Used on Command Mode : [10] [11] [12]
1918Display Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated