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Camera ISP Integration
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Table 6-17. Camera ISP CSI1/CCP2B Receiver Interrupt Details (continued)
Event Mask Description
CCP2_LC23_IRQSTATUS [26] CCP2_LC23_IRQENABLE [26] LC3_LE_IRQ Line-end synchronization code detection for
LC3_LE_IRQ logical channel 3:
This interrupt is triggered on the detection of a
line-end synchronization code into the CCP2 data
stream.
CCP2_LC23_IRQSTATUS [25] CCP2_LC23_IRQENABLE [25] LC3_LS_IRQ Line-start synchronization code detection for
LC3_LS_IRQ logical channel 3:
This interrupt is triggered on the detection of a
line-start synchronization code into the CCP2 data
stream.
CCP2_LC23_IRQSTATUS [24] CCP2_LC23_IRQENABLE [24] LC3_FE_IRQ Frame-end synchronization code detection for
LC3_FE_IRQ logical channel 3:
This interrupt is triggered on the detection of a
frame-end synchronization code into the CCP2
data stream.
CCP2_LC23_IRQSTATUS [23] CCP2_LC23_IRQENABLE [23] Frame counter reached for logical channel 3:
LC3_COUNT_IRQ LC3_COUNT_IRQ This interrupt is triggered when the frame counter
has reached its programmable target value.
CCP2_LC23_IRQSTATUS [21] CCP2_LC23_IRQENABLE [21] FIFO overflow error error for logical channel 3:
LC3_FIFO_OVF_IRQ LC3_FIFO_OVF_IRQ This interrupt is triggered upon detection of a
FIFO overflow. An overflow can occur if there is a
mismatch between the data input and output
rates.
CCP2_LC23_IRQSTATUS [20] CCP2_LC23_IRQENABLE [20] CRC error for logical channel 3:
LC3_CRC_IRQ LC3_CRC_IRQ This interrupt is triggered upon detection of a
mismatch between the transmitter and receiver
checksums. This interrupt does not apply to the
MIPI CSI1 compatible mode.
CCP2_LC23_IRQSTATUS [19] CCP2_LC23_IRQENABLE [19] False synchronization code protection error for
LC3_FSP_IRQ LC3_FSP_IRQ logical channel 3:
This interrupt is triggered by the FSP decoder if an
illegal combination is detected, but 0xA5 is not
present in the bit stream.
CCP2_LC23_IRQSTATUS [18] CCP2_LC23_IRQENABLE [18] LC3_FW_IRQ Frame-width error for logical channel 3:
LC3_FW_IRQ This interrupt is generated if the frame width
constraints associated to the current data type is
not respected.
CCP2_LC23_IRQSTATUS [17] CCP2_LC23_IRQENABLE [17] False synchronization code error for logical
LC3_FSC_IRQ LC3_FSC_IRQ channel 3:
This interrupt is triggered if the synchronization
code order is not respected. This state is shown in
the CCP2 receiver finite state machine.
CCP2_LC23_IRQSTATUS [16] CCP2_LC23_IRQENABLE [16] Shifted synchronization code error for logical
LC3_SSC_IRQ LC3_SSC_IRQ channel 3:
This interrupt is triggered if LEC or FEC are not
aligned on a 32-bit boundary. This state is shown
in the CCP2 receiver finite state-machine. The
shifted synchronization code error is highlighted in
the CCP2 receiver finite state-machine.
(3)
CCP2_LC23_IRQSTATUS [11] CCP2_LC23_IRQENABLE [11] LC2_FS_IRQ Frame-start synchronization code detection for
LC2_FS_IRQ logical channel 2:
This interrupt is triggered on the detection of a
frame-start synchronization code into the CCP2
data stream.
CCP2_LC23_IRQSTATUS [10] CCP2_LC23_IRQENABLE [10] LC2_LE_IRQ Line-end synchronization code detection detection
LC2_LE_IRQ for logical channel 2:
This interrupt is triggered on the detection of a
line-end synchronization code into the CCP2 data
stream.
(3)
This error can be triggered if the complex I/O cell is used in parallel output mode (CCP_CTRL[2]IO_OUT_SEL=1).
1150 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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