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Camera ISP Integration
Table 6-17. Camera ISP CSI1/CCP2B Receiver Interrupt Details (continued)
Event Mask Description
CCP2_LC01_IRQSTATUS [16] CCP2_LC01_IRQENABLE [16]LC1_SSC_IR Shifted synchronization code error for logical
LC1_SSC_IRQ Q channel 1:
This interrupt is triggered if LEC or FEC are not
aligned on a 32-bit boundary. This state is shown
in the CCP2 receiver finite state-machine. The
shifted synchronization code error is highlighted in
the CCP2 receiver finite state-machine.
(1)
CCP2_LC01_IRQSTATUS [11] CCP2_LC01_IRQENABLE [11] LC0_FS_IRQ Frame-start synchronization code detection for
LC0_FS_IRQ logical channel 0:
This interrupt is triggered on the detection of a
frame-start synchronization code into the CCP2
data stream.
CCP2_LC01_IRQSTATUS [10] CCP2_LC01_IRQENABLE [10] LC0_LE_IRQ Line-end synchronization code detection for
LC0_LE_IRQ logical channel 0:
This interrupt is triggered on the detection of a
line-end synchronization code into the CCP2 data
stream.
CCP2_LC01_IRQSTATUS [9] CCP2_LC01_IRQENABLE [9] LC0_LS_IRQ Line-start synchronization code detection for
LC0_LS_IRQ logical channel 0:
This interrupt is triggered on the detection of a
line-start synchronization code into the CCP2 data
stream.
CCP2_LC01_IRQSTATUS [8] CCP2_LC01_IRQENABLE [8] LC0_FE_IRQ Frame-end synchronization code detection for
LC0_FE_IRQ logical channel 0:
This interrupt is triggered on the detection of a
frame-end synchronization code into the CCP2
data stream.
CCP2_LC01_IRQSTATUS [7] CCP2_LC01_IRQENABLE [7] Frame counter reached for logical channel 0:
LC0_COUNT_IRQ LC0_COUNT_IRQ This interrupt is triggered on the frame counter
reached into the CCP2 data stream.
CCP2_LC01_IRQSTATUS [5] CCP2_LC01_IRQENABLE [5] FIFO overflow error for logical channel 0:
LC0_FIFO_OVF_IRQ LC0_FIFO_OVF_IRQ This interrupt is triggered on the detection of a
FIFO overflow error.
CCP2_LC01_IRQSTATUS [4] CCP2_LC01_IRQENABLE [4] LC0_CRC_IRQ CRC error
LC0_CRC_IRQ This interrupt is triggered on the detection of a
CRC error into the CCP2 data stream.
CCP2_LC01_IRQSTATUS [3] CCP2_LC01_IRQENABLE [3] LC0_FSP_IRQ False synchronization code protection error for
LC0_FSP_IRQ logical channel 0:
This interrupt is triggered by the FSP decoder if an
illegal combination is detected, but 0xA5 is not
present in the bit stream.
CCP2_LC01_IRQSTATUS [2] CCP2_LC01_IRQENABLE [2] LC0_FW_IRQ Frame-width error for logical channel 0:
LC0_FW_IRQ This interrupt is triggered on the detection of a
frame-width error into the CCP2 data stream.
CCP2_LC01_IRQSTATUS [1] CCP2_LC01_IRQENABLE [1] LC0_FSC_IRQ False synchronization code error for logical
LC0_FSC_IRQ channel 0:
This interrupt is triggered on the detection of a
false synchronization code error into the CCP2
data stream.
CCP2_LC01_IRQSTATUS [0] CCP2_LC01_IRQENABLE [0] LC0_SSC_IRQ Shifted synchronization code error for logical
LC0_SSC_IRQ channel 0:
This interrupt is triggered if LEC or FEC are not
aligned on a 32-bit boundary. This state is shown
in the CCP2 receiver finite state-machine. The
shifted synchronization code error is highlighted in
the CCP2 receiver finite state-machine.
(2)
CCP2_LC23_IRQSTATUS [27] CCP2_LC23_IRQENABLE [27] LC3_FS_IRQ Frame-start synchronization code detection for
LC3_FS_IRQ logical channel 3:
This interrupt is triggered on the detection of a
frame-start synchronization code into the CCP2
data stream
(1)
This error can be triggered if the complex I/O cell is used in parallel output mode (CCP_CTRL[2]IO_OUT_SEL=1).
(2)
This error can be triggered if the complex I/O cell is used in parallel output mode (CCP_CTRL[2]IO_OUT_SEL=1).
1149 SWPU177N – December 2009 – Revised November 2010 Camera Image Signal Processor
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