Texas Instruments OMAP36 Series, Техническое справочное руководство

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IVA2.2 Subsystem Register Manual
Table 5-628. VLCD_VLD_PREFIX_AC
Address Offset 0x0000 1104
Physical Address 0x0008 1104 Instance iVLCD
Description This register sets the ring buffer end address.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED NBITS_AC0 NBITS_AC1
RESERVED
Bits Field Name Description Type Reset
31:13 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
12:8 NBITS_AC0 Sets the number of prefix bits of control table for the RW 0x00
AC0 term as input to the UVLD.
7:5 RESERVED Write 0s for future compatibility RW 0x0
Read returns 0
4:0 NBITS_AC1 Sets the number of prefix bits of control table for the RW 0x00
AC1 term as input to the UVLD.
Table 5-629. Register Call Summary for Register VLCD_VLD_PREFIX_AC
IVA2.2 Subsystem Register Manual
• iVLCD Register Mapping Summary : [0]
Table 5-630. VLCD_WMV9_CONFIG
Address Offset 0x0000 1108
Physical Address 0x0008 1108 Instance iVLCD
Description This register controls the WMV9 parameters
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
QSCALE
PQUANT
BLNBSYM
INTRAFRT INTERFRT
RESERVED
Bits Field Name Description Type Reset
31:10 RESERVED Write 0s for future compatibility RW 0x00
Read returns 0
9:8 BLNBSYM Specifies the number of symbols in a block RW 0x0
0x0: 64
0x1: 32
0x2: 16
0x3: Reserved
7 RESERVED Write 0s for future compatibility. Read returns 0. RW 0x0
6 PQUANT Setting this bit to '1' specify: PQUANT>=8, I-Frame RW 0x0
5:4 QSCALE Quantization Scale RW 0x0
1033 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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