Timer_B Introduction
665
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Timer_B
26.1 Timer_B Introduction
Timer_B is a 16-bit timer/counter with up to seven capture/compare registers. Timer_B can support
multiple capture/compares, PWM outputs, and interval timing. Timer_B also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Timer_B features include:
•
Asynchronous 16-bit timer/counter with four operating modes and four selectable lengths
•
Selectable and configurable clock source
•
Up to seven configurable capture/compare registers
•
Configurable outputs with PWM capability
•
Double-buffered compare latches with synchronized loading
•
Interrupt vector register for fast decoding of all Timer_B interrupts
The block diagram of Timer_B is shown in
.
NOTE:
Use of the word count
Count
is used throughout this chapter. It means the counter must be in the process of
counting for the action to take place. If a particular value is directly written to the counter, an
associated action does not take place.
NOTE:
Nomenclature
There may be multiple instantiations of Timer_B on a given device. The prefix TBx is used,
where x is a greater than equal to zero indicating the Timer_B instantiation. For devices with
one instantiation, x = 0. The suffix n, where n = 0 to 6, represents the specific
capture/compare registers associated with the Timer_B instantiation.
26.1.1 Similarities and Differences From Timer_A
Timer_B is identical to Timer_A with the following exceptions:
•
The length of Timer_B is programmable to be 8, 10, 12, or 16 bits.
•
Timer_B TBxCCRn registers are double-buffered and can be grouped.
•
All Timer_B outputs can be put into a high-impedance state.
•
The SCCI bit function is not implemented in Timer_B.