Timer_A Registers
658
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Timer_A
25.3.1 TAxCTL Register
Timer_Ax Control Register
Figure 25-16. TAxCTL Register
15
14
13
12
11
10
9
8
Reserved
TASSEL
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
7
6
5
4
3
2
1
0
ID
MC
Reserved
TACLR
TAIE
TAIFG
rw-(0)
rw-(0)
rw-(0)
rw-(0)
rw-(0)
w-(0)
rw-(0)
rw-(0)
Table 25-4. TAxCTL Register Description
Bit
Field
Type
Reset
Description
15-10
Reserved
RW
0h
Reserved
9-8
TASSEL
RW
0h
Timer_A clock source select
00b = TAxCLK
01b = ACLK
10b = SMCLK
11b = INCLK
7-6
ID
RW
0h
Input divider. These bits along with the TAIDEX bits select the divider for the
input clock.
00b = /1
01b = /2
10b = /4
11b = /8
5-4
MC
RW
0h
Mode control. Setting MC = 00h when Timer_A is not in use conserves power.
00b = Stop mode: Timer is halted
01b = Up mode: Timer counts up to
10b = Continuous mode: Timer counts up to 0FFFFh
11b = Up/down mode: Timer counts up to
then down to 0000h
3
Reserved
RW
0h
Reserved
2
TACLR
RW
0h
Timer_A clear. Setting this bit clears TAR, the clock divider logic (the divider
setting remains unchanged), and the count direction. The TACLR bit is
automatically reset and is always read as zero.
1
TAIE
RW
0h
Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
0b = Interrupt disabled
1b = Interrupt enabled
0
TAIFG
RW
0h
Timer_A interrupt flag
0b = No interrupt pending
1b = Interrupt pending