0
4
8
12
1
5
3
2
6
9
7
15 14 13
11 10
0
4
8
12
1
5
3
2
6
9
7
13
11 10
OBR = 0, SHIFT = 0, DALGN = 0
Filter Output
SDHSDT Register
0
4
8
12
1
5
3
2
6
9
7
15 14 13
11 10
0
4
8
12
1
5
3
2
6
9
7
13
11 10
OBR = 0, SHIFT = 1, DALGN = 0
Filter Output
SDHSDT Register
0
4
8
12
1
5
3
2
6
9
7
15 14 13
11 10
0
4
8
12
1
5
3
2
6
9
7
13
11 10
OBR = 0, SHIFT = 2, DALGN = 0
Filter Output
SDHSDT Register
0
4
8
12
1
5
3
2
6
9
7
15 14 13
11 10
0
4
8
12
1
5
3
2
6
9
7
13
11 10
OBR = 1, SHIFT = 0, DALGN = 0
Filter Output
SDHSDT Register
0
4
8
12
1
5
3
2
6
9
7
15 14 13
11 10
0
4
8
12
1
5
3
2
6
9
7
13
11 10
OBR = 1, SHIFT = 1, DALGN = 0
Filter Output
SDHSDT Register
0
4
8
12
1
5
3
2
6
9
7
15 14 13
11 10
0
4
8
12
1
5
3
2
6
9
7
13
11 10
OBR = 2, SHIFT = 0, DALGN = 0
Filter Output
SDHSDT Register
SDHS Functional Operation
577
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
Sigma-Delta High Speed (SDHS)
Figure 22-13. Bits Selection From Filter to the Data Register (SDHSCTL0.DALGN = 0)