FRAM Controller A (FRCTL_A) Operation
300
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
FRAM Controller A (FRCTL_A)
8.2.2 Programming FRAM Memory Devices
There are three options for programming an MSP430 FRAM device. All options support in-system
programming.
•
Program with JTAG or the Spy-Bi-Wire interface
•
Program with the BSL
•
Program with a custom solution
8.2.2.1
Programming FRAM Memory With JTAG or Spy-Bi-Wire
Devices can be programmed through the JTAG port or the Spy-Bi-Wire port. The JTAG interface requires
access to TDI, TDO, TMS, TCK, TEST, ground, and optionally V
CC
and RST/NMI. Spy-Bi-Wire interface
requires access to TEST, RST/NMI, ground and optionally V
CC
. For more details, see the
Programming With the JTAG Interface
.
8.2.2.2
Programming FRAM Memory With the Bootstrap Loader (BSL)
Every device contains a BSL stored in ROM. The BSL enables users to read or program the FRAM or
RAM using a UART serial interface. Access to the FRAM through the BSL is protected by a 256-bit user-
defined password. For more details, see the
MSP430 Programming With the Bootloader (BSL)
8.2.2.3
Programming FRAM Memory With a Custom Solution
The ability of the CPU to write to its own FRAM allows for in-system and external custom programming
solutions. The user can choose to provide data to the device through any means available (for example,
UART or SPI). User-developed software can receive the data and program the FRAM. Because this type
of solution is developed by the user, it can be completely customized to fit the application needs for
programming or updating the FRAM.
8.2.3 Access Control
8.2.3.1
Write Protection
The WPROT bit can be used to protect the contents of FRAM from being unintentionally modified. When
the WPROT is set, reading is allowed, but no writing to FRAM memory is allowed. If a write access is
attempted with WPROT = 1, the WPIFG (write protection flag) bit is set. In this case, the error generates a
system NMI (SYSNMI) if the WPIE (write protection interrupt enable) bit is set. Note that writing-to-FRAM
is also blocked when the ACCTEIFG bit is set due to a timing violation. The WPIFG bit is set when a write
access is attempted with ACCTEIFG = 1.
The WPROT bit protects the entire FRAM from unintended writes regardless of MPU configurations, so
this bit should be used as temporary protection. To protect a portion of the FRAM permanently, use the
MPU module (see
,
Memory Protection Unit
). Write protection is disabled after BOR (WPROT =
0).
8.2.3.2
Two Wait State Modes
FRAM memory has limited access speed (see the device data sheet for details), but that does not limit the
speed of CPU and DMA in the device. When the running speed of the CPU and DMA exceeds the FRAM
access speed, a wait state control mechanism is implemented. The FRAM controller A (FRCTL_A)
supports two wait state modes, user wait state mode and automatic wait state mode.
8.2.3.3
User Wait State Mode
User wait state mode and automatic wait state mode are mutually exclusive. User wait state mode is
automatically enabled after device reset (BOR), but the wait state mode can be switched to automatic wait
state mode by setting the AUTO bit. The FRAM access speed can be maximized in user wait state mode
by writing an optimized wait state number to NWAITS[3:0]. However, incorrect wait state numbers may
cause a timing violation error. Thus, the application must write a proper wait state to NWAITS[3:0] before
accessing FRAM. See
for optimized wait states with different system frequencies.