MPY32 Registers
287
SLAU367P – October 2012 – Revised April 2020
Copyright © 2012–2020, Texas Instruments Incorporated
32-Bit Hardware Multiplier (MPY32)
5.3.1 MPY32CTL0 Register
32-Bit Hardware Multiplier Control 0 Register
Figure 5-6. MPY32CTL0 Register
15
14
13
12
11
10
9
8
Reserved
MPYDLY32
MPYDLYWRTEN
r-0
r-0
r-0
r-0
r-0
r-0
rw-0
rw-0
7
6
5
4
3
2
1
0
MPYOP2_32
MPYOP1_32
MPYMx
MPYSAT
MPYFRAC
Reserved
MPYC
rw
rw
rw
rw
rw-0
rw-0
rw-0
rw
Table 5-9. MPY32CTL0 Register Description
Bit
Field
Type
Reset
Description
15-10
Reserved
R
0h
Reserved. Always reads as 0.
9
MPYDLY32
RW
0h
Delayed write mode
0b = Writes are delayed until 64-bit result (RES0 to RES3) is available.
1b = Writes are delayed until 32-bit result (RES0 to RES1) is available.
8
MPYDLYWRTEN
RW
0h
Delayed write enable
All writes to any MPY32 register are delayed until the 64-bit (MPYDLY32 = 0) or
32-bit (MPYDLY32 = 1) result is ready.
0b = Writes are not delayed.
1b = Writes are delayed.
7
MPYOP2_32
RW
0h
Multiplier bit width of operand 2
0b = 16 bits
1b = 32 bits
6
MPYOP1_32
RW
0h
Multiplier bit width of operand 1
0b = 16 bits
1b = 32 bits
5-4
MPYMx
RW
0h
Multiplier mode
00b = MPY – Multiply
01b = MPYS – Signed multiply
10b = MAC – Multiply accumulate
11b = MACS – Signed multiply accumulate
3
MPYSAT
RW
0h
Saturation mode
0b = Saturation mode disabled
1b = Saturation mode enabled
2
MPYFRAC
RW
0h
Fractional mode
0b = Fractional mode disabled
1b = Fractional mode enabled
1
Reserved
RW
0h
Reserved. Always reads as 0.
0
MPYC
RW
0h
Carry of the multiplier. It can be considered as 33rd or 65th bit of the result if
fractional or saturation mode is not selected, because the MPYC bit does not
change when switching to saturation or fractional mode.
It is used to restore the SUMEXT content in MAC mode.
0b = No carry for result
1b = Result has a carry