ADC10_B Operation
16.2.2.1 Analog Port Selection
The ADC10_B inputs are multiplexed with digital port pins. When analog signals are applied to digital
gates, parasitic current can flow from V
CC
to GND. This parasitic current occurs if the input voltage is near
the transition level of the gate. Disabling the digital part of the port pin eliminates the parasitic current flow
and, therefore, reduces overall current consumption. The PySELx bits provide the ability to disable the
port pin input and output buffers.
; Py.0 and Py.1 configured for analog input
BIS.B #3h,&PySEL ; Py.1 and Py.0 ADC10_B function
16.2.3 Voltage Reference Generator
The ADC10_B module is designed to be used either with the on-chip reference supplied by the REF
module or an externally reference voltage supplied on external pins.
The on-chip reference is capable of supplying 1.5 V, 2.0 V and 2.5 V. The internal V
CC
can also be used
as the voltage reference. Refer to the REF chapter for details on the operation of this internal reference.
External references may be supplied for V
R+
and V
R-
through pins VREF+/VEREF+ and VREF-/VEREF- ,
respectively.
16.2.3.1 Internal Reference Low-Power Features
The on-chip reference is designed for low-power applications. This reference includes a band-gap voltage
source and a separate reference buffer, both of which are located in the REF module. The current
consumption of each is specified separately in the device-specific data sheet. The ADC10_B also contains
an internal buffer for reference voltages. This buffer is automatically enabled when the internal reference
is selected for V
REF+
, but it is also optionally available for Ve
REF+
. The on-chip reference from the REF
module must be enabled by software. Its settling time is
≤
30 µs. See the REF module description for
further information on the on-chip reference.
The reference buffer of the ADC10_B also has selectable speed versus power settings. When the
maximum conversion rate is below 50 ksps, setting ADC10SR = 1 reduces the current consumption of the
buffer by approximately 50%.
16.2.4 Auto Power Down
The ADC10_B is designed for low-power applications. When the ADC10_B is not actively converting, the
core is automatically disabled. It is automatically reenabled when needed. The MODOSC is also
automatically enabled when needed and disabled when not needed.
16.2.5 Sample and Conversion Timing
An analog-to-digital conversion is initiated with a rising edge of the sample input signal SHI. The source
for SHI is selected with the ADC10SHSx bits and can be any of the following:
•
ADC10SC bit
•
On of three timer outputs
The polarity of the SHI signal source can be inverted with the ADC10ISSH bit. The SAMPCON signal
controls the sample period and start of conversion. When SAMPCON is high, sampling is active. The high-
to-low SAMPCON transition starts the analog-to-digital conversion, which requires 11 ADC10CLK cycles
in 10-bit resolution mode. One additional ADC10CLK is used for the window comparator. Two different
sample-timing methods are defined by control bit ADC10SHP: extended sample mode and pulse mode.
16.2.5.1 Extended Sample Mode
The extended sample mode is selected when ADC10SHP = 0. The SHI signal directly controls SAMPCON
and defines the length of the sample period t
sample.
When SAMPCON is high, sampling is active. The high-
to-low SAMPCON transition starts the conversion after synchronization with ADC10CLK (see
437
SLAU272C – May 2011 – Revised November 2013
ADC10_B Module
Copyright © 2011–2013, Texas Instruments Incorporated