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Mates to AWR RF Board P1

AWR1_CSI

58

FPGA1_DPHY0_CLK_P
FPGA1_DPHY0_CLK_N
FPGA1_DPHY0_D0_P
FPGA1_DPHY0_D0_N
FPGA1_DPHY0_D1_P
FPGA1_DPHY0_D1_N
FPGA1_DPHY0_D2_P
FPGA1_DPHY0_D2_N
FPGA1_DPHY0_D3_P
FPGA1_DPHY0_D3_N

AWR1_CSI

AWR2_CSI

58

FPGA2_DPHY0_CLK_P
FPGA2_DPHY0_CLK_N
FPGA2_DPHY0_D0_P
FPGA2_DPHY0_D0_N
FPGA2_DPHY0_D1_P
FPGA2_DPHY0_D1_N
FPGA2_DPHY0_D2_P
FPGA2_DPHY0_D2_N
FPGA2_DPHY0_D3_P
FPGA2_DPHY0_D3_N

AWR2_CSI

FPGA1_DPHY0_D0_P

FPGA1_DPHY0_D0_N

FPGA1_DPHY0_D1_P

FPGA1_DPHY0_D1_N

FPGA1_DPHY0_D2_P

FPGA1_DPHY0_D2_N

FPGA1_DPHY0_D3_P

FPGA1_DPHY0_D3_N

FPGA1_DPHY0_CLK_P

58

I2C3

FPGA1_DPHY0_CLK_N

TDA_I2C3_SCL

TDA_I2C3_SDA

TDA_I2C3_SCL

I2C3

TDA_I2C3_SDA

58

UART_AWR1

58

UART_AWR2

TDA_UART1_TXD
TDA_UART1_RXD

UART_AWR1

TDA_UART2_TXD
TDA_UART2_RXD

UART_AWR2

58

AWR_SOP0

58

AWR_SOP1

58

AWR_SOP2

58

AWR_WARM_RST

58

AWR1_RESETN

58

AWR2_RESETN

TDA_UART3_AWR1_RXD

TDA_UART3_AWR1_TXD

TDA_UART3_AWR2_TXD

TDA_UART3_AWR2_RXD

AWR_ERROR_OUTN

58

AWR2_SPI_SCLK

AWR2_SPI_CS0N

AWR2_SPI_MOSI

AWR2_SPI_MISO

AWR1_SPI_CS0N

AWR1_SPI_MOSI

AWR1_SPI_MISO

AWR1_SPI_SCLK

58

AWR1_SPI_SCLK

58

AWR1_SPI_CS0N

58

AWR1_SPI_MOSI

58

AWR1_SPI_MISO

58

AWR2_SPI_SCLK

58

AWR2_SPI_CS0N

58

AWR2_SPI_MOSI

58

AWR2_SPI_MISO

Net Class i

ClassName: AWR1_SPI

Net Class i

ClassName: AWR2_SPI

58

AWR1_SPI_INT

58

AWR2_SPI_INT

FPGA2_DPHY0_D0_P

FPGA2_DPHY0_D0_N

FPGA2_DPHY0_D1_P

FPGA2_DPHY0_D1_N

FPGA2_DPHY0_D2_P

FPGA2_DPHY0_D2_N

FPGA2_DPHY0_D3_P

FPGA2_DPHY0_D3_N

FPGA2_DPHY0_CLK_P

FPGA2_DPHY0_CLK_N

TDA_GPIO2_2_AWR1_RESETN

TDA_GPIO2_9_AWR2_RESETN

TDA_GPIO7_24_AWR1_SPI_INT

TDA_GPIO2_19_AWR_ERROR_OUTN

TDA_GPIO2_22_AWR_SOP0

TDA_GPIO2_25_AWR_SOP1

TDA_GPIO2_13_AWR_SOP2

TDA_GPIO2_12_AWR_WARM_RST

P1

P3

MH1

MH3

P2

P4

MH2

MH4

1

10

11

2
3
4
5
6
7
8
9

12
13
14
15
16
17
18
19
20

21

22
23
24
25
26
27
28
29
30

31

32
33
34
35
36
37
38
39
40

41

42
43
44
45
46
47
48
49
50

51

52
53
54
55
56
57
58
59
60

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

J1

GND

Hirose_FX23-120S-0_5SV10

GND

AWR_CONN1_MON

AWR_CONN_TP1

TP1

AWR_CONN_TP2

TP4

TP5

AWR_CONN_TP3

FPGA1_DPHY0_D0_P

FPGA1_DPHY0_D0_N

FPGA1_DPHY0_D1_P

FPGA1_DPHY0_D1_N

FPGA1_DPHY0_D2_P

FPGA1_DPHY0_D2_N

FPGA1_DPHY0_D3_P

FPGA1_DPHY0_D3_N

FPGA2_DPHY0_CLK_P

FPGA2_DPHY0_CLK_N

FPGA2_DPHY0_D0_P

FPGA2_DPHY0_D0_N

FPGA2_DPHY0_D1_P

FPGA2_DPHY0_D1_N

FPGA2_DPHY0_D2_P

FPGA2_DPHY0_D2_N

FPGA2_DPHY0_D3_P

FPGA2_DPHY0_D3_N

FPGA1_DPHY0_CLK_P

FPGA1_DPHY0_CLK_N

58

TDA_AWR1_GPIO2

58

TDA_AWR1_GPIO1

58

TDA_AWR1_GPIO0

AWR_EXT_DIG_SYNC

AWR_CONN1_MON

AWR1_SPI_MISO

AWR1_SPI_CS0N

TDA_GPIO7_24_AWR1_SPI_INT

AWR1_SPI_MOSI

AWR1_SPI_SCLK

TDA_I2C3_SCL

TDA_I2C3_SDA

TP3

AWR_CONN_TP5

TDA_GPIO2_19_AWR_ERROR_OUTN

TDA_UART3_AWR1_TXD

TDA_UART3_AWR1_RXD

AWR1_SOP2

0

R1

TDA_GPIO2_13_AWR_SOP2

AWR1_SOP1

0

R2

TDA_GPIO2_25_AWR_SOP1

AWR1_SOP0

0

R3

TDA_GPIO2_22_AWR_SOP0

0

R4

TDA_GPIO2_2_AWR1_RESETN

AWR1_WARM_RST

TDA_GPIO2_12_AWR_WARM_RST

AWR2_SPI_MISO

AWR2_SPI_CS0N

AWR2_SPI_MOSI

AWR2_SPI_SCLK

TDA_UART3_AWR2_TXD

TDA_UART3_AWR2_RXD

TDA_GPIO2_9_AWR2_RESETN

AWR2_WARM_RST

TDA_GPIO2_12_AWR_WARM_RST

AWR2_SOP2

TDA_GPIO2_13_AWR_SOP2

AWR2_SOP1

TDA_GPIO2_25_AWR_SOP1

0

AWR2_SOP0

R5

0

TDA_GPIO2_22_AWR_SOP0

R6

0

R7

0

R8

10V

47uF

C2

GND

47uF
10V

C1

GND

SYSTEM_5V0

TDA_AWR1_GPIO0_GPIO4_18

TDA_AWR1_GPIO1_GPIO6_4

TDA_AWR1_GPIO2_GPIO6_5

TDA_AWR2_SPI_INT_GPIO5_10

TDA_AWR2_SPI_INT_GPIO5_10

AWR_EXT_DIG_SYNC

58

AWR_EXT_DIG_SYNC

TP191
TP192

AWR1_MSS_LOGGER

AWR1_BSS_LOGGER

AWR2_MSS_LOGGER

TP193

AWR2_BSS_LOGGER

TP194

Design Note: TDA I2C3 interfaces
to primary AWR PMIC I2C port.

Design Note: FROM AWR devices

Design Note: TO AWR devices

Design Note: TO AWR devices

Design Note: FROM AWR devices

www.ti.com

Hardware Specifications

9

SPRUIS6 – September 2019

Submit Documentation Feedback

Copyright © 2019, Texas Instruments Incorporated

MMWCAS-DSP-EVM

Figure 7. DSP Host to RF Board Connector #1 (J1)

Table 1. DSP Host to RF Board Connector Pin Table (J1)

Host Board Connector 1 (J1) - Mated to RF Board P1

Pin Number

Net Name

Pin Type

Function/Description

1

CONN_MON

Passive

Connector monitor

2

TP1

Passive

Test Point

3

GND

Power

System ground return

4

NC

None

Unused

5

NC

None

Unused

6

GND

Power

System ground return

7

GND

Power

System ground return

8

NC

None

Unused

9

NC

None

Unused

10

GND

Power

System ground return

11

GND

Power

System ground return

12

AWR1_D3_P

Input

AWR #1 CSI2 TX3

13

AWR1_D3_N

Input

AWR #1 CSI2 TX3

14

GND

Power

System ground return

15

GND

Power

System ground return

16

AWR1_D2_P

Input

AWR #1 CSI2 TX2

17

AWR1_D2_N

Input

AWR #1 CSI2 TX2

18

GND

Power

System ground return

19

AWR1_CLK_P

Input

AWR #1 CSI2 Clock

20

AWR1_CLK_N

Input

AWR #1 CSI2 Clock

21

GND

Power

System ground return

22

TP4

Passive

Test point

23

GND

Power

System ground return

Содержание MMWCAS-DSP-EVM

Страница 1: ...lab Post Processing 19 List of Figures 1 Caution Hot Surface Warning located on EVM 3 2 MMWCAS DSP EVM Functional Block Diagram 4 3 MMWCAS DSP EVM Front 5 4 MMWCAS DSP EVM Back 6 5 MMWCAS DSP EVM bottom and MMWCAS RF EVM top Board Alignment 7 6 System Power Distribution Network 8 7 DSP Host to RF Board Connector 1 J1 9 8 DSP Host to RF Board Connector 2 J18 12 9 FPGA Flash Programming Header Pinou...

Страница 2: ...aces with a companion Cascade Radar EVM MMWCAS RF EVM The MMWCAS RF EVM is a 4 device cascaded array of AWR1243P mmWave devices This user guide references the MMWCAS RF EVM and Radar Board as the same items Both boards together provide a full Radar system evaluation 1 1 Key Features The key features of the MMWCAS DSP EVM are TDA2SX ADAS SoC 23 mm 23 mm Four Lattice Crosslink Automotive Grade FPGAs...

Страница 3: ...assembled on EVM 16GB microSD Card Ethernet cable Power Cable assembly USBA to miniB Cable Mounting standoffs and screws 1 3 Thermal Compliance There is elevated heat on the processor heatsink use caution at elevated ambient temperature Although the processor heatsink is not a burn hazard caution should be used when handling the EVM due to increased heat in the area of the heatsink Figure 1 Cautio...

Страница 4: ...ry 2Gbyte Total Hirose FX23 120S 0 5SV10 AWR1243 RF Board Connectors CSI2 0 AWR 1 CSI2 0 AWR 2 CSI2 0 AWR 3 CSI2 0 AWR 3 UART3 1 4 MUX UART AWR 1 UART AWR 2 UART AWR 3 UART AWR 4 SPI1 SPI3 SPI AWR 1 4 SPI AWR 2 3 GPIO SOP ERROR UART USB Bridge USB2 0 Mini Connector UART1 USB3 0 Device Connector USB3 0 Super Speed 5Gbps EMU Port VOUT 60 Pin MIPI Debug Header EMU DP83867IRPAPR 1G Ethernet PHY RGMII ...

Страница 5: ...s Instruments Incorporated MMWCAS DSP EVM 2 2 Board Dimensions Description The MMWCAS DSP EVM dimensions are 160 mm 136 mm It is a 22 layer board fabricated with epoxy fiberglass UL94V 0 Certified Figure 3 and Figure 4 show the top and bottom layers with key components identified Figure 3 MMWCAS DSP EVM Front ...

Страница 6: ... connector Cascade RF board connector Cascade RF board connector PCIe m 2 SSD connector and screw hole Hardware Specifications www ti com 6 SPRUIS6 September 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated MMWCAS DSP EVM Figure 4 MMWCAS DSP EVM Back ...

Страница 7: ...ecure a single assembly of the boards Refer to Figure 5 for reference Figure 5 MMWCAS DSP EVM bottom and MMWCAS RF EVM top Board Alignment 2 4 Power The MMWCAS DSP EVM is powered by 12 V power either from a DC barrel connector J10 or screw terminal J11 A wall DC power source or a bench power source can be used to power the EVM The power source should be rated at least 3 A The typical power source ...

Страница 8: ...5V 4A Load Expected 12V 5 0V 3 3V LP5907QMFX 2 5Q1 LDO x FPGA 2 5V TPS62262TDRVRQ1 LDO x FPGA 1 2V Hardware Specifications www ti com 8 SPRUIS6 September 2019 Submit Documentation Feedback Copyright 2019 Texas Instruments Incorporated MMWCAS DSP EVM Figure 6 System Power Distribution Network 2 5 Connectors 2 5 1 RF Board Connectors J1 J18 The primary board to board connectors on the EVM J1 and J18...

Страница 9: ...GA1_DPHY0_D3_N FPGA2_DPHY0_CLK_P FPGA2_DPHY0_CLK_N FPGA2_DPHY0_D0_P FPGA2_DPHY0_D0_N FPGA2_DPHY0_D1_P FPGA2_DPHY0_D1_N FPGA2_DPHY0_D2_P FPGA2_DPHY0_D2_N FPGA2_DPHY0_D3_P FPGA2_DPHY0_D3_N FPGA1_DPHY0_CLK_P FPGA1_DPHY0_CLK_N 58 TDA_AWR1_GPIO2 58 TDA_AWR1_GPIO1 58 TDA_AWR1_GPIO0 AWR_EXT_DIG_SYNC AWR_CONN1_MON AWR1_SPI_MISO AWR1_SPI_CS0N TDA_GPIO7_24_AWR1_SPI_INT AWR1_SPI_MOSI AWR1_SPI_SCLK TDA_I2C3_S...

Страница 10: ..._P Input AWR 2 CSI2 TX3 42 AWR2_D3_N Input AWR 2 CSI2 TX3 43 GND Power System ground return 44 GND Power System ground return 45 AWR2_D2_P Input AWR 2 CSI2 TX2 46 AWR2_D2_N Input AWR 2 CSI2 TX2 47 GND Power System ground return 48 GND Power System ground return 49 AWR2_CLK_P Input AWR 2 CSI2 Clock 50 AWR2_CLK_N Input AWR 2 CSI2 Clock 51 GND Power System ground return 52 TP5 Passive 53 GND Power Sy...

Страница 11: ...OP1 signal 84 AWR_SOP_TDO Output AWR 1 TDO SOP0 signal 85 AWR1_RESETn Output AWR 1 NRESET signal 86 AWR_WARM_RST Output AWR 1 WARM_RESET signal 87 GND Power System ground return 88 NC Passive 89 NC Passive 90 NC Passive 91 NC Passive 92 GND Power System ground return 93 SPI3_MISO Input AWR 2 SPI Slave MISO 94 AWR2_SPI_INT AWR 2 SPI Slave Interrupt 95 GND Power System ground return 96 AWR2_CS0n Out...

Страница 12: ...SPI_MOSI AWR4_SPI_CS0N AWR4_SPI_MISO AWR3_WARM_RST AWR3_SOP0 AWR3_SOP1 AWR3_SOP2 AWR3_SPI_SCLK AWR3_SPI_MOSI AWR3_SPI_CS0N AWR3_SPI_MISO AWR4_SOP2 AWR4_SOP0 AWR4_SOP1 AWR4_WARM_RST TDA_UART3_AWR4_RXD TDA_UART3_AWR4_TXD TDA_UART3_AWR3_RXD TDA_UART3_AWR3_TXD TDA_GPIO7_25_AWR4_SPI_INT TDA_GPIO2_22_AWR_SOP0 TDA_GPIO2_25_AWR_SOP1 TDA_GPIO2_13_AWR_SOP2 TDA_GPIO2_22_AWR_SOP0 TDA_GPIO2_25_AWR_SOP1 TDA_GPI...

Страница 13: ..._SCLK Output AWR 4 SPI Slave SCLK 24 SPI1_MOSI Output AWR 4 SPI Slave MOSI 25 AWR4_CS1n Output AWR 4 SPI Slave SCLK 26 GND Power System ground return 27 AWR4_SPI_INT Input AWR 4 SPI Slave Interrupt 28 SPI1_MISO Input AWR 4 SPI Slave MISO 29 GND Power System ground return 30 NC Passive 31 NC Passive 32 NC Passive 33 NC Passive 34 GND Power System ground return 35 AWR_WARM_RST Output AWR 3 WARM_RESE...

Страница 14: ...ND Power System ground return 69 TP_SP1 Passive Test Point 183 70 GND Power System ground return 71 AWR4_CLK_N Input AWR 4 CSI2 Clock 72 AWR4_CLK_P Input AWR 4 CSI2 Clock 73 GND Power System ground return 74 GND Power System ground return 75 AWR4_D2_N Input AWR 4 CSI2 TX2 76 AWR4_D2_P Input AWR 4 CSI2 TX2 77 GND Power System ground return 78 GND Power System ground return 79 AWR4_D3_N Input AWR 4 ...

Страница 15: ...ystem ground return 112 NC Passive 113 NC Passive 114 GND Power System ground return 115 GND Power System ground return 116 NC Passive 117 NC Passive 118 GND Power 119 PWR_GOOD Input Power good from RF 120 CONN2_MON Passive Connector connection monitor unused 121 EVM_5V0 Power 122 EVM_5V0 Power 123 GND Power System ground return 124 GND Power System ground return 125 GND Power System ground return...

Страница 16: ...ds 8 kV IEC 61000 4 2 direct contact The DP83867 provides precision clock synchronization including a synchronous Ethernet clock output It has low latency and provides IEEE 1588 Start of Frame Detection 2 5 4 PCIe m 2 socket m keyed J14 The DSP EVM supports PCIe 2 0 through an m 2 connector Out of the box a 512 GB SSD is assembled on the EVM The connector is a JAE Electronics SM3ZS067U410AMR1000 P...

Страница 17: ...pullup on board 0 Active 1 Inactive Default GPIO_EXP_P13 PERST PCIe Reset functional reset to the card 0 Hold in reset until stable Default 1 Release from reset GPIO_EXP_P14 CLKREQ PCIe Reference Clock Request 0 Request for clock 1 Not Active Default GPIO6_8 Selects between AWR and FPGA Flash for SPI1 0 Selects AWR Default 1 Selects FPGA Flash GPIO6_6 When ganged Controls FPGA1 2 3 4 CRESETN signa...

Страница 18: ...wer is applied Refer to the SCH for resistor options in order to toggle ON OFF functionality S2 PORz Reset Generates a PORz reset upon pushing S3 SoC Reset Generates a reset on the SoC 2 6 4 LEDs The MMWCAS DSP EVM supports LEDs for user indications as listed in Table 7 Table 7 User and Status LED Reference Designator and Description Reference Usage Description Color D3 Status Ethernet Activity Gr...

Страница 19: ...atus TPS51200 DDR3 VTT and VREF Power Good Green D27 Status FPGA4 LED Green 3 mmWave Studio and Matlab Post Processing TI provides the following evaluation software to get started with the Cascade DSP evaluation module mmWave Studio GUI and Lua scriptable configuration environment TDA2x ADC IF data capture application running on the MMWCAS DSP EVM Matlab post processing sample codes for reading ca...

Страница 20: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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