Texas Instruments LP876242-Q1, Руководство пользователя

Страница: 7 / 29

Figure 3-2. EVM Bottom Side
Table 3-6. DC Block
Measurement point BUCK1 BUCK2 BUCK3 BUCK4
After second LC stage
(Filtered) (default) C15 C42 C59 C66
Before second LC stage
(Unfiltered) C10 C36 C58 C65
Two load module connector footprints are provided, J1 and J2. These connectors are intended to be used
with PMICLOADBOARDEVM which is sold separately. The connector components are not populated and the
required connectors are shipped with PMICLOADBOARDEVM.
3.5 DIP Switches
There are three DIP switches S1, S2 and S3 on the back side of the PCB. S1 switch can be used for configuring
chip select for target device in multi PMIC/stacked use case. S2 and S3 switches allow the user to disconnect
the level shifter from the PMIC GPIOs or serial interfaces. The level shifter has pull-ups on the MCU side that
can cause unwanted high state on the GPIO signals if configured in high impedance state. See the
Table 3-7 for
the descriptions of the switches.
www.ti.com EVM Details
SLVUC20A – MARCH 2021 – REVISED AUGUST 2022
Submit Document Feedback
LP876242-Q1 Evaluation Module 7
Copyright © 2022 Texas Instruments Incorporated