Texas Instruments LP38798EVM, Руководство пользователя, Страница: 3 / 11

IN
EN
CP
GND (CP)
OUT
SET
FB
GND
OUT
OUT (FB)
IN
IN (CP)
Exposed Pad on
Bottom
(DAP)
1
2
3
4
5
6 7
8
9
10
11
12
OUT(FB)
2
3
4
5
6
7
8
1
SET
FB
GND(CP)
CP
EN
IN(CP)
V
IN
V
OUT
GND GND
R1
R2
LP38798SD-ADJ
GND
IN
IN
OUT
OUT
9
10
11
12
V
EN
DAP
+
+
C2
C1
C3
C4
C5
TP1 TP2
TP3
TP4
TP5
J1
J5
J2
J3 J4
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Setting the Output Voltage
Target V
OUT
R1 R2 Typical V
OUT
3.00V 22.6 k
Ω
15.0 k
Ω
3.008V
3.30V 26.1 k Ω 15.0 k Ω 3.288V
4.70V 44.2 k Ω 15.0 k Ω 4.736V
5.00V 47.5 k Ω 15.0 k Ω 5.000V
Figure 1. LP38798EVM Schematic
Figure 2. LP38798SD-ADJ (12-lead WSON) Connection Diagram
Figure 3. Top Layer as Viewed from Top
3 SNOA914 – March 2013 LP38798EVM User's Guide
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