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Texas Instruments LMX2572LPEVM Скачать руководство пользователя страница 18

Bill of Materials

www.ti.com

18

SNAU235 – May 2018

Submit Documentation Feedback

Copyright © 2018, Texas Instruments Incorporated

LMX2572LPEVM Evaluation Instructions

6

Bill of Materials

Table 6. Bill of Materials

DESIGNATOR

QUANTITY DESCRIPTION

PART NUMBER

MANUFACTURER

C1, C3, C9, C14, C15, C17, C19, C30

8

CAP, CERM, 0.1 µF, 16 V, ±5%, X7R,
0603

0603YC104JAT2A

AVX

C2, C4, C8, C16

4

CAP, CERM, 10 µF, 10 V, ±10%, X5R,
0805

C0805C106K8PACTU

Kemet

C2_LF

1

CAP, CERM, 0.015 µF, 50 V, ±10%,
X7R, 0603

GRM188R71H153KA01D

MuRata

C4_LF

1

CAP, CERM, 2200 pF, 50 V, ±5%,
C0G/NP0, 0603

GRM1885C1H222JA01D

MuRata

C5, C7, C10, C12

4

CAP, CERM, 0.01 µF, 16 V, ±10%, X7R,
0402

520L103KT16T

AT Ceramics

C18, C23, C26, C27, C28, C29

6

CAP, CERM, 1 µF, 16 V, ±10%, X7R,
0603

C1608X7R1C105K080AC

TDK

C20, C21, C22

3

CAP, CERM, 10 µF, 10 V, ±20%, X5R,
0603

C1608X5R1A106M080AC

TDK

C24

1

CAP, CERM, 0.01 µF, 50 V, ±5%, X7R,
0603

C0603C103J5RACTU

MuRata

C25

1

CAP, CERM, 0.47 µF, 25 V, ±10%, X7R,
0603

GRM188R71E474KA12D

Kemet

CE_TP, CSB_TP, GND_TP,
MUXout_TP, RampCLK_TP,
RampDIR_TP, SCK_TP, SDI_TP,
SYNC_TP, SysRefReq_TP, Vcc_TP,
VccRF_TP, Vtune_TP

13

Test Point, Compact, White, TH

5007

Keystone

Cin_0

1

CAP, CERM, 10 µF, 25 V, ±10%, X5R,
0805

GRM219R61E106KA12D

MuRata

Cout0

1

CAP, CERM, 22 µF, 16 V, ±10%, X5R,
0805

C2012X5R1C226K125AC

TDK

Css

1

CAP, CERM, 3300 pF, 50 V, ±5%,
C0G/NP0, 0603

GRM1885C1H332JA01D

MuRata

D1

1

LED, Green, SMD

LTST-C190GKT

Lite-On

L1_TPS

1

Inductor, Shielded, Composite, 2.2 µH,
3.7 A, 0.02

Ω

, SMD

XFL4020-222MEB

Coilcraft

MUXout_SW

1

Switch, SPST, Slide, Off-On, 2 Pos, 0.1
A, 20 V, SMD

219-2MST

CTS
Electrocomponents

OSCinM, OSCinP, SYNC, SysRef, Vcc

5

Connector, SMT, End launch SMA 50

Ω

142-0701-851

Emerson Network
Power Connectivity

R1

1

RES, 330

Ω

, 5%, 0.1 W, 0603

RC0603JR-07330RL

Yageo America

R2

1

RES, 100 k

Ω

, 5%, 0.1 W, 0603

CRCW0603100KJNEA

Vishay-Dale

R2_LF

1

RES, 330

Ω

, 5%, 0.1 W, 0603

CRCW0603330RJNEA

Vishay-Dale

R3_LF, R4_LF, R12, R15, R24, R26,
R31

7

RES, 0

Ω

, 5%, 0.1 W, 0603

CRCW06030000Z0EA

Vishay-Dale

R5, R7, R8, R9, R16, R19, R20, R22

8

RES, 12 k

Ω

, 5%, 0.1 W, 0603

CRCW060312K0JNEA

Vishay-Dale

R25, R30

2

RES, 51

Ω

, 5%, 0.1 W, 0603

CRCW060351R0JNEA

Vishay-Dale

R34, R35, R36, R41, R42, R43, R44,
R45

8

RES, 0

Ω

, 5%, 0.1 W, 0603

CRCW06030000Z0EA

Vishay-Dale

Rfbb1

1

RES, 180 k

Ω

, 0.1%, 0.1 W, 0603

RT0603BRD07180KL

Yageo America

Rfbt1

1

RES, 562 k

Ω

, 1%, 0.1 W, 0603

CRCW0603562KFKEA

Vishay-Dale

RFoutAM, RFoutAP, RFoutBM, RFoutBP

4

JACK, SMA, 50

Ω

, Gold, Edge Mount

142-0771-831

Johnson

U1

1

High Performance, Wideband PLLatinum
RF Synthesizer

LMX2572LPRHAR

Texas Instruments

uWire

1

Header (shrouded), 100 mil, 5x2, Gold
plated, SMD

52601-S10-8LF

FCI

Содержание LMX2572LPEVM

Страница 1: ...e any frequency from 12 5 MHz to 2 GHz without using an internal VCO doubler The PLL delivers excellent performance while consuming just 70 mA from a single 3 3 V supply Contents 1 LMX2572LPEVM Evaluation Module 3 2 Setup 3 3 Typical Measurement 6 4 Schematic 13 5 PCB Layout and Layer Stack Up 15 6 Bill of Materials 18 7 Troubleshooting Guide 19 Appendix A Using Different Reference Clock 20 Append...

Страница 2: ...22 Power Layer 16 23 Bottom Layer 17 24 Troubleshooting Guide 19 25 Output Termination Schematic 22 26 Default Output Phase Nosie 23 27 Default Output Waveform 23 28 Firmware Requirement 23 29 Firmware Loader 24 30 BSL Button 24 31 Update Firmware 25 32 Firmware Update Complete 25 33 USB Communications 26 List of Tables 1 Loop Filter Configuration 6 2 Phase Adjustment Setting 7 3 Calibration free ...

Страница 3: ...ribbon cable 1 2 Evaluation Setup Requirement The evaluation requires the following hardware and software A DC power supply A spectrum analyzer or a signal analyzer A PC running Windows 7 or more recent version An oscilloscope optional A high quality signal generator optional Texas Instruments Clocks and Synthesizers TICS Pro software Texas Instruments PLLatinum Simulator Tool optional 1 3 Resourc...

Страница 4: ...ired the EVM can be modified to operate with a different clock source in a different configuration See Appendix A for more details Terminate the unused output of the Reference PRO board with a 50 Ω resistor or SMA load By default the output clock from the Reference PRO is a 100 MHz LVPECL clock Appendix B has the details of the Reference PRO 2 4 RF Output Connect either the RFoutAP or RFoutAM SMA ...

Страница 5: ...lect Device PLL VCO LMX2572 LMX2572LP Figure 2 Select Device in TICS Pro 2 Go to Default Configuration Default Mode YYYY MM DD Figure 3 Default Mode 2 7 EVM Strap Options 2 7 1 MUXout_SW There are two switches in MUXout_SW Switch 1 is used for register readback while Switch 2 is used to provide a visual PLL lock status through the LED D1 By default both switches are in the Make position To read ba...

Страница 6: ...p Filter Configuration PARAMETER VALUE VCO frequency Designed for 6 GHz but works over the whole frequency range VCO gain 66 MHz V Effective charge pump gain 2500 µA Phase detector frequency 100 MHz Loop bandwidth 115 kHz Phase margin 48 degrees C1_LF C3_LF Open C2_LF 15 nF C4_LF 2 2 nF R2_LF 330 Ω R3_LF R4_LF 0 Ω Figure 5 Loop Filter 3 1 2 Typical Output 1 Follow Section 2 to set up the evaluatio...

Страница 7: ...on 1 to adjust the phase of the RF output signal Phase shift in degree 360 MASH_SEED PLL_DEN P CHDIV where P 2 when VCO_PHASE_SYNC_EN 1 otherwise P 1 1 Table 2 and Equation 2 show an example Table 2 Phase Adjustment Setting PARAMETER EXAMPLE VALUE MASH_SEED 800 PLL_DEN 1000 CHDIV 32 VCO_PHASE_SYNC_EN 0 Phase shift 360 800 1000 1 32 9 2 The user can write 800 to MASH_SEED 40 times to get the 360 ph...

Страница 8: ...limited When using ramp these parameters must be set accordingly OUT_FORCE 1 LD_DLY 0 PLL_DEN 232 1 Table 3 Calibration free Automatic Ramp Example PARAMETER EXAMPLE VALUE Ramping start frequency 4795 MHz Ramping stop frequency 4805 MHz Phase detector frequency 50 MHz Ramp up down time 200 µs RAMP_LIMIT_HIGH 4995 MHz RAMP_LIMIT_LOW 4595 MHz This is a triangular ramp example Ramp up is defined by R...

Страница 9: ... ramping mode supports wider ramp frequency but there are glitches in the middle of the ramp because of the VCO calibrations that are required to ensure the continuity of the ramp Table 4 Automatic Ramp Example PARAMETER EXAMPLE VALUE Ramping start frequency 4740 MHz Ramping stop frequency 4860 MHz Phase detector frequency 50 MHz Ramp up down time 1000 µs RAMP_LIMIT_HIGH 5060 MHz RAMP_LIMIT_LOW 45...

Страница 10: ... 4 3 2 4 FSK Modulation The LMX2572LP supports direct digital FSK modulation The FSK SPI mode supports discrete 2 4 or 8 level FSK modulation while the FSK SPI FAST and FSK I2S modes support arbitrary level FSK modulation Table 5 shows a FSK SPI FAST mode example Table 5 FSK SPI FAST Mode Example PARAMETER EXAMPLE VALUE Phase detector frequency 100 MHz CHDIV 8 PLL_DEN 8000000 FSK_DEV_SCALE 1 Frequ...

Страница 11: ...k Copyright 2018 Texas Instruments Incorporated LMX2572LPEVM Evaluation Instructions Write the correct values to the FSK_SPI_FAST_DEV register field The output of LMX2572LP is a discrete 4 level FSK modulation signal Figure 13 FSK SPI FAST Mode Setting Figure 14 FSK SPI FAST Mode ...

Страница 12: ... Register Readback To read back the written register values follow these steps 1 Set MUXout_SW Switch 2 to Break position See Section 2 7 1 for details 2 Set MUXOUT_LD_SEL to Readback in TICS Pro Figure 15 Readback Setting 3 Click on the Register Name that you want to read back 4 Click the Read Register button to read back the register value Figure 16 Register Readback ...

Страница 13: ...w ti com Schematic 13 SNAU235 May 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMX2572LPEVM Evaluation Instructions 4 Schematic Figure 17 LMX2572LPEVM Schematic Page 1 ...

Страница 14: ...Schematic www ti com 14 SNAU235 May 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMX2572LPEVM Evaluation Instructions Figure 18 LMX2572LPEVM Schematic Page 2 ...

Страница 15: ...CB Layout and Layer Stack Up 15 SNAU235 May 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMX2572LPEVM Evaluation Instructions 5 PCB Layout and Layer Stack Up 5 1 PCB Layer Stack Up The top layer is 1 oz copper Figure 19 PCB Layer Stack Up 5 2 PCB Layout Figure 20 Top Layer ...

Страница 16: ...out and Layer Stack Up www ti com 16 SNAU235 May 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMX2572LPEVM Evaluation Instructions Figure 21 GND Layer Figure 22 Power Layer ...

Страница 17: ...www ti com PCB Layout and Layer Stack Up 17 SNAU235 May 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated LMX2572LPEVM Evaluation Instructions Figure 23 Bottom Layer ...

Страница 18: ...D MuRata Cout0 1 CAP CERM 22 µF 16 V 10 X5R 0805 C2012X5R1C226K125AC TDK Css 1 CAP CERM 3300 pF 50 V 5 C0G NP0 0603 GRM1885C1H332JA01D MuRata D1 1 LED Green SMD LTST C190GKT Lite On L1_TPS 1 Inductor Shielded Composite 2 2 µH 3 7 A 0 02 Ω SMD XFL4020 222MEB Coilcraft MUXout_SW 1 Switch SPST Slide Off On 2 Pos 0 1 A 20 V SMD 219 2MST CTS Electrocomponents OSCinM OSCinP SYNC SysRef Vcc 5 Connector S...

Страница 19: ...ation No Yes Verify communications x R WR 86 RPPXQLFDWLRQV QWHUIDFH ensure that the USB2ANY button is turned green OLFN GHQWLI WR have the program blink the green LED x Send simple one way communication to the device such as POWERDOWN RESET or change the status of a pin Realize that if a RESET is done do a Ctrl L to refresh the registers afterwards For POWERDOWN you can validate this looking at th...

Страница 20: ...lock Appendix A SNAU235 May 2018 Using Different Reference Clock These are the different options to provide a reference clock to LMX2572LPEVM By default the EVM is configured for an external single ended clock Table 7 Reference Clock Input Configuration INPUT EXTERNAL CLOCK CRYSTAL OSCILLATOR Single ended Differential LVDS ...

Страница 21: ...ugh the jumpers by strapping the center pin to Vdd position or GND position Connections from the Vdd position to the device supply or from the GND position to the ground plane are connected by 1 5 kΩ resistors By default the board is configured for 100 MHz LVPECL output Connect the Reference PRO to the PC through the USB interface to provide the Reference PRO a steady power supply B 1 Output Frequ...

Страница 22: ...le 10 1 50 Ω to VCC 2 V termination is required on receiver 2 100 Ω differential termination R31 is provided onboard Removing this termination is possible if the differential termination is available on the receiver Table 10 Output Termination Configuration OUTPUT FORMAT COUPLING COMPONENT VALUE LVPECL AC Default configuration R15 R28 0 Ω R26 R29 150 Ω C24 C25 0 01 µF R27 R30 R31 DNP DC 1 R15 R28 ...

Страница 23: ...Waveform B 4 Firmware Update Usually when the Reference PRO board is used at the first time TICS Pro will request a firmware update Follow the pop up instructions to complete the update This update is necessary to ensure that the USB connection between the PC and the Reference PRO board is properly set up otherwise the programming to LMX2572LPEVM will not be successful 1 When you see this message ...

Страница 24: ... May 2018 Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Reference PRO 2 Next follow the on screen procedure Figure 29 Firmware Loader 3 The BSL button is located next to the USB connector Figure 30 BSL Button ...

Страница 25: ...Texas Instruments Incorporated Reference PRO 4 Follow the on screen procedure until the Update Firmware button pops up Figure 31 Update Firmware 5 Click the Upgrade Firmware button to start the upgrade and click the Close button after the upgrade is complete Figure 32 Firmware Update Complete ...

Страница 26: ... Submit Documentation Feedback Copyright 2018 Texas Instruments Incorporated Reference PRO 6 Check the USB connection in TICS Pro by clicking USB communications Interface Make sure that the USB Connected button is green Figure 33 USB Communications ...

Страница 27: ...y set forth above or credit User s account for such EVM TI s liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty If TI elects to repair or replace such EVM TI shall have a reasonable time to repair such EVM or provide replacements Repaired EVMs shall be warr...

Страница 28: ...the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated Antenna types not included in this list having a gain greater than the maximum gain indicated for that type are strictly prohibited for use with this device Concernant les EVMs avec antennes détachables Conformément à la réglementation d Industrie Canada le présent émetteur radio peut fo...

Страница 29: ...ed loads Any loads applied outside of the specified output range may also result in unintended and or inaccurate operation and or possible permanent damage to the EVM and or interface electronics Please consult the EVM user guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation even ...

Страница 30: ...COST OF REMOVAL OR REINSTALLATION ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES RETESTING OUTSIDE COMPUTER TIME LABOR COSTS LOSS OF GOODWILL LOSS OF PROFITS LOSS OF SAVINGS LOSS OF USE LOSS OF DATA OR BUSINESS INTERRUPTION NO CLAIM SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE 12 MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED 8 2 Specif...

Страница 31: ... TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI product...

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